NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond

Takeshi HAMAMOTO; Yutaka ISHIBASHI; Masami AOKI; Yoshihiko SAITOH; Takashi YAMADA

NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond

Takeshi HAMAMOTO, Yutaka ISHIBASHI, Masami AOKI, Yoshihiko SAITOH, Takashi YAMADA

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NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm², which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.7 pp.789-796

Publication Date: 1995/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)

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Takeshi HAMAMOTO, Yutaka ISHIBASHI, Masami AOKI, Yoshihiko SAITOH, Takashi YAMADA, "NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 7, pp. 789-796, July 1995, doi: .
Abstract: NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm², which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e78-c_7_789/_p

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@ARTICLE{e78-c_7_789,
author={Takeshi HAMAMOTO, Yutaka ISHIBASHI, Masami AOKI, Yoshihiko SAITOH, Takashi YAMADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond},
year={1995},
volume={E78-C},
number={7},
pages={789-796},
abstract={NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm², which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - NAND-Structured Trench Capacitor Cell Technologies for 256 Mb DRAM and Beyond
T2 - IEICE TRANSACTIONS on Electronics
SP - 789
EP - 796
AU - Takeshi HAMAMOTO
AU - Yutaka ISHIBASHI
AU - Masami AOKI
AU - Yoshihiko SAITOH
AU - Takashi YAMADA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1995
AB - NAND-structured trench capacitor cell technologies for 256 Mb DRAM and beyond have been developed. The NAND-structured cell has four memory cells connected in series. The cell size can be reduced to 56% of the conventional cell. A substrate plate trench capacitor cell was adapted to this layout. The NAND-structured trench capacitor cell can achieve sufficient storage capacitance within the restricted capacitor area. A sufficient capacitance of 40 fF was achieved when the size and depth of trench were 0.5 µm and 5.0 µm, respectively. The most important point for realizing the NAND-structured trench capacitor cell is how to reduce the leakage current from the storage node. There are two main sources; one is the leakage current to the neighboring cells, the other is the leakage current to Pwell. These leakage currents have been investigated. An experimental 256 Mb DRAM with the NAND-structured cell was fabricated using the 0.4 µm design rule. The chip size is 464 mm², which is 68% of a conventional DRAM of the same design rule. This is the result of the reduction of the memory cell area by the NAND-structured cell and the introduction of the open-bit-line arrangement.
ER -