A charge-integration read scheme has been developed for a solid-nanopore DNA-sequencer that determines a genome by direct and electrical measurements of transverse tunneling current in single-stranded DNA. The magnitude of the current was simulated with a first-principles molecular dynamics method. It was found that the magnitude is as small as in the sub-pico ampere range, and signals from four bases represent wide distributions with overlaps between each base. The distribution is believed to originate with translational and rotational motion of DNA in a nanopore with a frequency of over 105 Hz. A sequence scheme is presented to distinguish the distributed signals. The scheme makes widely distributed signals time-integrated convergent by cumulating charge at the capacitance of a nanopore device and read circuits. We estimated that an integration time of 1.4 ms is sufficient to obtain a signal difference of over 10 mV for distinguishing between each DNA base. Moreover, the time is shortened if paired bases, such as A-T and C-G in double-stranded DNA, can be measured simultaneously with two nanopores. Circuit simulations, which included the capacitance of a nanopore calculated with a device simulator, successfully distinguished between DNA bases in less than 2.0 ms. The speed is roughly six orders faster than that of a conventional DNA sequencer. It is possible to determine the human genome in one day if 100-nanopores are operated in parallel.

A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-VT PMOS amplifier and a low-VT NMOS amplifier which is composed of high-VT NMOSs and a low-VT cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-VT CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.