Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

Akira KOTABE; Riichiro TAKEMURA; Yoshimitsu YANAGAWA; Tomonori SEKIGUCHI; Kiyoo ITOH

doi:10.1587/transele.E95.C.594

Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays

Akira KOTABE, Riichiro TAKEMURA, Yoshimitsu YANAGAWA, Tomonori SEKIGUCHI, Kiyoo ITOH

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A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-V_T PMOS amplifier and a low-V_T NMOS amplifier which is composed of high-V_T NMOSs and a low-V_T cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-V_T CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-V_T NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.

Publication: IEICE TRANSACTIONS on Electronics Vol.E95-C No.4 pp.594-599

Publication Date: 2012/04/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E95.C.594

Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)

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Akira KOTABE, Riichiro TAKEMURA, Yoshimitsu YANAGAWA, Tomonori SEKIGUCHI, Kiyoo ITOH, "Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays" in IEICE TRANSACTIONS on Electronics, vol. E95-C, no. 4, pp. 594-599, April 2012, doi: 10.1587/transele.E95.C.594.
Abstract: A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-V_T PMOS amplifier and a low-V_T NMOS amplifier which is composed of high-V_T NMOSs and a low-V_T cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-V_T CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-V_T NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.594/_p

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@ARTICLE{e95-c_4_594,
author={Akira KOTABE, Riichiro TAKEMURA, Yoshimitsu YANAGAWA, Tomonori SEKIGUCHI, Kiyoo ITOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays},
year={2012},
volume={E95-C},
number={4},
pages={594-599},
abstract={A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-V_T PMOS amplifier and a low-V_T NMOS amplifier which is composed of high-V_T NMOSs and a low-V_T cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-V_T CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-V_T NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.},
keywords={},
doi={10.1587/transele.E95.C.594},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays
T2 - IEICE TRANSACTIONS on Electronics
SP - 594
EP - 599
AU - Akira KOTABE
AU - Riichiro TAKEMURA
AU - Yoshimitsu YANAGAWA
AU - Tomonori SEKIGUCHI
AU - Kiyoo ITOH
PY - 2012
DO - 10.1587/transele.E95.C.594
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-V_T PMOS amplifier and a low-V_T NMOS amplifier which is composed of high-V_T NMOSs and a low-V_T cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-V_T CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-V_T NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.
ER -