We developed a Nb 4-layer process for fabricating superconducting integrated circuits that involves using caldera planarization to increase the flexibility and reliability of the fabrication process. We call this process the planarized high-speed standard process (PHSTP). Planarization enables us to flexibly adjust most of the Nb and SiO2 film thicknesses; we can select reduced film thicknesses to obtain larger mutual coupling depending on the application. It also reduces the risk of intra-layer shorts due to etching residues at the step-edge regions. We describe the detailed process flows of the planarization for the Josephson junction layer and the evaluation of devices fabricated with PHSTP. The results indicated no short defects or degradation in junction characteristics and good agreement between designed and measured inductances and resistances. We also developed single-flux-quantum (SFQ) and adiabatic quantum-flux-parametron (AQFP) logic cell libraries and tested circuits fabricated with PHSTP. We found that the designed circuits operated correctly. The SFQ shift-registers fabricated using PHSTP showed a high yield. Numerical simulation results indicate that the AQFP gates with increased mutual coupling by the planarized layer structure increase the maximum interconnect length between gates.

The three-bit balanced ternary quantum voltage generator was designed and tested. This voltage generator is based on zero-crossing Shapiro steps (ZCSSs) in asymmetric two-junction SQUID. ZCSSs were observed on the current-voltage curves, and maximum and minimum current of ZCSSs were almost same, respectively for the three bits. 27-step quantum voltages from -13Φ0f to +13 Φ0f were observed by combinations of inputs of bit1, bit2 and bit3.

We numerically simulated electrical properties, i.e., the resistance and Coulomb blockade threshold, of randomly-placed conductive nanoparticles. In simulation, tunnel junctions were assumed to be formed between neighboring particle-particle and particle-electrode connections. On a plane of triangle 100×100 grids, three electrodes, the drain, source, and gate, were defined. After random placements of conductive particles, the connection between the drain and source electrodes were evaluated with keeping the gate electrode disconnected. The resistance was obtained by use of a SPICE-like simulator, whereas the Coulomb blockade threshold was determined from the current-voltage characteristics simulated using a Monte-Carlo simulator. Strong linear correlation between the resistance and threshold voltage was confirmed, which agreed with results for uniform one-dimensional arrays.

We present two types of ICF (INHIBIT Controlled by Fluxon) gates as the basic circuits of the phase-mode logic family, and fabricate an adder circuit. The experimental result demonstrates that the carry operation followed up to 99 GHz input pulses. The performance of Josephson devices is improved by the use of junctions with high current density (Jc). We may use the high-Jc junctions without external resistive shunt in the phase-mode logic circuits because of reduction of the junction hysteresis. One of the ways to overcome the large area occupancy for geometric inductance is to utilize the effective inductance of a Josephson junction itself. We investigate a circuit construction with high-Jc inductor junctions, intrinsically overdumped junctions and junction-type resistors for the compactness of circuit integration, and discuss various aspects of the circuit construction.

We present a superconducting neural network which functions as an RS flip-flop. We employ a coupled-SQUID as a neuron, which is a combination of a single-junction SQUID and a double-junction SQUID. A resistor is used as a fixed synapse. The network consists of two neurons and two synapses. The operation of the network is simulated under the junction current density of 100 kA/cm2. The result shows that the network is operated as an RS flip-flop with clock speed capability up to 50 GHz.

We present analytical and numerical results on the flux-quantum transitions in a three-junction superconducting quantum interference device (3J-SQUID) controlled by two RF signals. The 3J-SQUID has two superconducting loops, and the RF signals are magnetically coupled to the loops. Flux-quantum transitions in the 3J-SQUID loops can be controlled by utilizing the phase difference of the two RF signals. Under proper conditions, we can obtain a situation where one flux quantum passes through the 3J-SQUID per one cycle of the RF signals without DC current biasing, which results in a zero-crossing step on the current-voltage characteristics. In this paper, we first explain the operation principle by using a quantum state diagram of a 3J-SQUID. Next, we numerically simulate RF-induced transitions of the quantum states. A zero-crossing step on the current-voltage characteristics is demonstrated. We also investigate dependence of zero-crossing steps upon parameters of the 3J-SQUID and RF signals.

We experimentally evaluated random number sequences generated by a superconducting hardware random number generator composed of a Josephson-junction oscillator, a rapid-single-flux-quantum (RSFQ) toggle flip-flop (TFF), and an RSFQ AND gate. Test circuits were fabricated using a 10 kA/cm2 Nb/AlOx/Nb integration process. Measurements were conducted in a liquid helium bath. The random numbers were generated for a trigger frequency of 500 kHz under the oscillating Josephson-junction at 29 GHz. 26 random number sequences of 20 kb length were evaluated for bias voltages between 2.0 and 2.7 mV. The NIST FIPS PUBS 140-2 tests were used for the evaluation. 100% pass rates were confirmed at the bias voltages of 2.5 and 2.6 mV. We found that the Monobit test limited the pass rates. As numerical simulations suggested, a detailed evaluation for the probability of obtaining “1” demonstrated the monotonical dependence on the bias voltage.

A readout technique using single-flux-quantum (SFQ) circuits enables superconducting single photon detectors (SSPDs) to operate at further high-speed, where a mutually-coupled dc-to-SFQ (MC-dc/SFQ) converter is used as an interface between SSPDs and SFQ circuits. In this work, we investigated pulse response of the MC-dc/SFQ converter. We employed on-chip pulse generators to evaluate pulse response of the MC-dc/SFQ converter for various pulses. The MC-dc/SFQ converter correctly operated for the pulse current with the amplitude of 52,$mu$A and the width of 179,ps. In addition, we examined influence of the pulse amplitude and width to operation of the MC-dc/SFQ converter by numerical simulation. The simulation results indicated that the MC-dc/SFQ converter had wide operation margins for pulse current with amplitudes of 30--60,$mu$A irrespective of the pulse widths.

We numerically demonstrated the improvement of single-electron (SE) digital logic gates by utilizing SE input discretizers (IDs). The parameters of the IDs were adjusted to achieve SE tunneling at the threshold voltage designed for switching. An SE four-junction inverter (FJI) with an ID (ID-FJI) had steep switching characteristics between the high and low output voltage levels. The limiting temperature and the critical parameter margins were evaluated. An SE NAND gate with IDs also achieved abrupt switching characteristics between output logic levels.

Superconducting integrated circuits should be operated at low temperature below a half of their critical temperatures. Thermal heat from a bias resistor could rise the temperature in Josephson junctions, and would reduce their critical currents. In this study, we estimate the temperature in a Josephson junction heated by a bias resistor at the bath temperature of 4.2 K, and introduce a parameter β that connects the thermal heat from a bias resistor and the temperature elevation of a Josephson junction. By using β, the temperature in the Josephson junction can be estimated as functions of the current through the resistor.

Although larger scale integration enhances the practicability of superconducting Josephson circuits, several technical problems begin to emerge during its progress. One of the problems is the increase of current through a ground plane (ground current). Excess ground current produces additional magnetic field and reduces operation margins of the circuits, because superconducting Josephson devices are very sensitive to magnetic field. In this paper, we evaluate current distribution in a superconducting ground plane by means of both experiments and numerical calculation. We also verify two methods for suppressing the ground current. One is a slot structure in the ground plane, and the other is alignment of the current-extraction point. Suppression of the ground current is quantitatively evaluated.

Recently, we demonstrated a rapid-single-flux-quantum NOT gate comprising a toggle storage loop. In this paper, we present our design and operation of a NOR gate that is a straightforward extension of the NOT gate by attaching a confluence buffer. Parameter margins wider than ±28% were confirmed in simulation. Functional tests using Nb integrated circuits demonstrated correct NOR operation with a bias margin of ±21%.

Analysis of the operation modes of an RF-Field-Driven DC-SQUID (RFDS) is presented. We numerically calculate the current-voltage characteristics (IVC) of the RFDS, where the RF signal is coupled to the SQUID loop magnetically. Under no DC offset flux, the IVC exhibit the enhancement of the even-order steps. We first evaluate the dependence of the maximum 2nd step height of the RFDS upon frequency. Contrary to the results for a single junction, the RFDS maintains its step height at a certain value in the low frequency region. The maintained values of the maximum step height are dependent on βL. The smaller βL is, the larger the maximum step height becomes. Next, we evaluate the dependence of the current positions of the 2nd step upon the amplitude of the RF signal. Under the low frequency condition, the current positions agree with the interference patterns of the SQUID, which means that the operation of the RFDS is based on the quantum transitions in the SQUID loop. Under the high frequency condition, on the other hand, the current positions agree with the results for the single junction, which means that the quantum transitions does not follow the RF signal and that the RFDS behaves like a single junction.

A voltage mode logic device based on RF-Field-driven DC-SQUID (RFDS) using high-TC superconducting Josephson junctions has been proposed. RFDS produces large RF-induced steps, and the orders of steps are strongly selected by DC magnetic flux crossing the SQUID loop superposing with RF magnetic field. In this paper, we present the experimental results of RFDS fabricated by using YBCO grain boundary Josephson junctions. The results are evaluated with numerical simulations. The enhancement of RF-induced steps, the strong selection of step orders and the switching performance are demonstrated.

Gold nanoparticles (GNPs) are often used as island electrodes of single-electron (SE) devices. One of technical challenges in fabrication of SE devices with GNPs is the placement of GNPs in a nanogap between two lead electrodes. Utilization of dielectrophoresis (DEP) phenomena is one of possible solutions for this challenge, whereas the fabrication process with DEP includes stochastic aspects. In this brief paper, we present our experimental results on electric resistance of GNP arrays assembled by DEP. More than 300 pairs of electrodes were investigated under various DEP conditions by trial and error approach. We evaluated the relationship between the DEP conditions and the electric resistance of assembled GNP arrays, which would indicate possible DEP conditions for fabrication of SE devices.

A binary counter circuit in the extended phase-mode logic (EPL) family is presented. The EPL family utilizes a single flux quantum as an information bit carrier. Numerical simulations show that a binary counter circuit with a Josephson critical current density of 1 kA/cm2 can operate up to a 30 GHz input signal. The circuit has been fabricated using Nb/AlOx/Nb Josephson junction technology. New interface circuits are employed in the fabricated chip. A low speed test result shows the correct operation of the binary counter.

We present analytical expression for inductance of a superconducting stripline, a strip sandwiched by two superconducting ground planes. In our method, we utilize the analytical formula for a perfect-conducting stripline derived by Chang in 1976. To utilize Chang's formula, we first transform the structure of a superconducting stripline into that of a perfect-conducting stripline by reducing the thicknesses of the superconducting layers. The thickness reduction is "λ coth (t/λ)" for each (upper or lower) side, where λ and t are the field penetration depth and the layer thickness, respectively. Then, we apply Chang's formula to the transformed stripline model. The calculated results are in good agreement with the numerical and experimental results.

We present our design and operation of a 6-bit quasi-triangle voltage waveform generator comprising three circuit blocks; an improved variable Pulse Number Multiplier (variable-PNM), a Code Generator (CG), and a Double-Flux-Quantum Amplifier (DFQA). They are integrated into a single chip using a niobium Josephson junction technology. While the multiplication factor of our previous m-bit variable-PNM was limited between 2m-1 and 2m, that of the improved one is extended between 1 and 2m. Correct operations of the 6-bit variable-PNM are confirmed in low-speed testing with respect to the codes from the CG, whereas generation of a 6-bit, 0.20mVpp quasi-triangle voltage waveform is demonstrated with the 10-fold DFQA in high-speed testing.

The threshold characteristics of mutually coupled SQUIDs (Superconducting Quantum Interference Devices) have been analytically and numerically investigated. The mutually coupled SQUIDs investigated is composed of an rf-SQUID and a dc-SQUID. Here, the rf-SQUID is a flux quantum generator and the dc-SQUID is a flux detector. The linearization method substituting sin-1x by (π/2)x (1x1) is found valid when it is applied to the mutually coupled SQUIDs, because it is possible to obtain the superconducting regions analytically. By computer implementation of linearization method, we found this method is very effective and very quick compared to the ordinary methods. We report the internal flux on an rf-SQUID, the threshold of a dc-SQUID, and that of mutually coupled SQUIDs obtained by Lagrange multiplier formulation and linearization. The features of the threshold characteristics of the mutually coupled SQUIDs with various parameters are also reported. The discontinuous behavior of threshold of the mutually coupled SQUIDs are attractive for digital applications. We suggest three applications of the mutually coupled SQUIDs, that is, a logic gate for high-Tc superconductors (HTSs), a neuron device, and an A/D converter.