Author Search Result
[Author] Yoshiyuki HARAGUCHI(2hit)
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An Analysis of Substrate Current in Memory Cell for ULSI SRAM
Yoshiyuki HARAGUCHI Shuji MURAKAMI Yasumasa NISHIMURA Kenji ANAMI
- LETTER-Integrated Circuits
- Vol:
- E73-E No:11
- Page(s):
- 1861-1862
We analyze the substrate corrent of submicron transistors in the memory cell of ULSI SRAMs in the cases of PMOS and NMOS bit line loads. The lifetime of the transistors is also estimated. The SRAM using an NMOS bit load is found to be better as a hot carrier than that with a PMOS bit load.
A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die
Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA
- PAPER-Static RAMs
- Vol:
- E79-C No:6
- Page(s):
- 743-749
This paper describes a new hierarchical bit line organization utilizing a T-shaped bit line(H-BLT) and its practical implementation in a 4-Mb SRAM using a 0.4µm CMOS process. The H-BLT has reduced the number of I/O circuits for multiplexers, sense amplifiers and write drivers, resulting in an efficient multiple blockdivision of the memory cell array. The size of the SRAM die was reduced by 14% without an access penalty. The active current is 30mA at 5 V and 10 MHz. The typical address access time is 35 ns with a 4.5 V supply voltage and a 30 pF load capacitance. The operating voltage range is 2.5 V to 6.0 V. H-BLT is a bright and useful architecture for the high density SRAMs of the future.
