This paper investigates limitations of adjacent channel power ratio (ACPR) improvement in predistortion (pre-D) linearizer used with nonlinear RF power amplifiers (PAs) when the PA model is not perfectly acquired in pre-D design. The error between the physical PA and the nonlinear model is expanded by pre-D function and its power spectral density (PSD) works as limitations in ACPR improvement of the pre-D linearizer. An analytical estimation of ACPR limitations in RF PAs driven by digitally modulated input signal is derived using a formulation of autocorrelation function. The analysis technique is validated with the example of the memory polynomial PA model with the quasi-memoryless pre-D linearizer. The technique is also verified by comparing predicted ACPR limitation with measured limitation for a RF PA with 802.11g input signal.

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. To change the bandwidth, the charge pump current and the loop filter zero resistor should be changed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 µs and the phase noise is -121 dBc/ at 600 kHz offset. This chip is fabricated with 0.25 µm CMOS technology, and the die area is 0.7 mm2.1mm. The power consumption is 54 mW at 2.7 V supply voltage.