A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications

Kang-Yoon LEE; Hyunchul KU; Young Beom KIM

doi:10.1093/ietele/e89-c.3.420

A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications

Kang-Yoon LEE, Hyunchul KU, Young Beom KIM

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This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. To change the bandwidth, the charge pump current and the loop filter zero resistor should be changed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 µs and the phase noise is -121 dBc/ at 600 kHz offset. This chip is fabricated with 0.25 µm CMOS technology, and the die area is 0.7 mm2.1mm. The power consumption is 54 mW at 2.7 V supply voltage.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.420-428

Publication Date: 2006/03/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.3.420

Type of Manuscript: PAPER

Category: Integrated Electronics

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Kang-Yoon LEE, Hyunchul KU, Young Beom KIM, "A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 3, pp. 420-428, March 2006, doi: 10.1093/ietele/e89-c.3.420.
Abstract: This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. To change the bandwidth, the charge pump current and the loop filter zero resistor should be changed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 µs and the phase noise is -121 dBc/ at 600 kHz offset. This chip is fabricated with 0.25 µm CMOS technology, and the die area is 0.7 mm2.1mm. The power consumption is 54 mW at 2.7 V supply voltage.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.420/_p

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@ARTICLE{e89-c_3_420,
author={Kang-Yoon LEE, Hyunchul KU, Young Beom KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications},
year={2006},
volume={E89-C},
number={3},
pages={420-428},
abstract={This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. To change the bandwidth, the charge pump current and the loop filter zero resistor should be changed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 µs and the phase noise is -121 dBc/ at 600 kHz offset. This chip is fabricated with 0.25 µm CMOS technology, and the die area is 0.7 mm2.1mm. The power consumption is 54 mW at 2.7 V supply voltage.},
keywords={},
doi={10.1093/ietele/e89-c.3.420},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - A Fast Switching Low Phase Noise CMOS Frequency Synthesizer with a New Coarse Tuning Method for PHS Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 420
EP - 428
AU - Kang-Yoon LEE
AU - Hyunchul KU
AU - Young Beom KIM
PY - 2006
DO - 10.1093/ietele/e89-c.3.420
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. To change the bandwidth, the charge pump current and the loop filter zero resistor should be changed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. The proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about 20 µs and the phase noise is -121 dBc/ at 600 kHz offset. This chip is fabricated with 0.25 µm CMOS technology, and the die area is 0.7 mm2.1mm. The power consumption is 54 mW at 2.7 V supply voltage.
ER -