Multicast ATM switches are essential to support various types of services in the Broadband ISDN. In this paper we present an efficient architecture to support multicasting in shared buffer ATM switches. A lookahead technique is employed to resolve the head-of-line blocking problem in the multicast-queue approach, thus improving the throughput of the multicast traffic. The arbitration between multicast and unicast services is investigated to prevent the lookahead technique from increasing the multicast dominance. We show through performance and complexity comparisons that with a small hardware overhead over the multicast-queue approach, our architecture provides a throughput performance comparable to address-duplication or searchable-queue-based approaches.

A new pixel design and driving method for active matrix organic light emitting diode (AMOLED) displays that use low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with a voltage programming method are proposed and verified using the SPICE simulator. We had employed an appropriate TFT model in SPICE simulation to demonstrate the performance of the pixel circuit. The OLED anode voltage variation error rates are below 0.35% under driving TFT threshold voltage deviation (Δ Vth = 0.33 V). The OLED current non-uniformity caused by the OLED threshold voltage degradation (Δ VTO = +0.33 V) is significantly reduced (below 6%). The simulation results show that the pixel design can improve the display image non-uniformity by compensating for the threshold voltage deviation in the driving TFT and the OLED threshold voltage degradation at the same time.

This paper presents an efficient queue manager chip for controlling a 16 16 shared buffer ATM switch with a 256-cell buffer. Compared to conventional implementations of queue managers for shared buffer ATM switches, our design eliminates the idle address FIFO and the pre-allocated bubbles at the tails of output queues. The former reduces the storage size required for queue management, while the latter improves the effective buffer capacity. Such modular implementation also provides flexibilities in queue management implementation. Back-pressure with soft-full and hard-full flow control for multi-stage expansion and two priority classes with push-out cell discarding are supported without extra hardware overhead. This chip was designed and fabricated using 0.8µm CMOS technology. It has 35,700 transistors in a chip area of 28.3mm2, with a core of 10.4mm2and 32,960 transistors. Two test sequences were developed during the design phase to fully verify the queue management functions of the prototype chip. The queue manager chip was tested up to 36 MHz, and is able to control a 16 16 shared buffer switch with a 155 MHz link rate.