This work reports a new technique to suppress the undesirable multiple-triggering effect in the typical diode triggered silicon controlled rectifier (DTSCR), which is frequently used as an ESD protection element in the advanced CMOS technologies. The technique is featured by inserting additional N-Well areas under the N+ region of intrinsic SCR, which helps to improve the substrate resistance. As a consequence, the delay of intrinsic SCR is reduced as the required triggering current is largely decreased and multiple-triggering related higher trigger voltage is removed. The novel DTSCR structures can alter the stacked diodes to achieve the precise trigger voltage to meet different ESD protection requirements. All explored DTSCR structures are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and Very-Fast-Transmission-line-pulsing (VF-TLP) test systems are adopted to confirm the validity of this technique and the test results accord well with our analysis.

Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.

The write operations on emerging Non-Volatile Memory (NVM), such as NAND Flash and Phase Change Memory (PCM), usually incur high access latency, and are required to be optimized. In this paper, we propose Asymmetric Read-Write (ARW) policies to minimize the write traffic sent to NVM. ARW policies exploit the asymmetry costs of read and write operations, and make adjustments on the insertion policy and hit-promotion policy of the replacement algorithm. ARW can reduce the write traffic to NVM by preventing dirty data blocks from frequent evictions. We evaluate ARW policies on systems with PCM as main memory and NAND Flash as disk. Simulation results on an 8-core multicore show that ARW adopted on the last-level cache (LLC) can reduce write traffic by more than 15% on average compared to LRU baseline. When used on both LLC and DRAM cache, ARW policies achieve an impressive reduction of 40% in write traffic without system performance degradation. When employed on the on-disk buffer of the Solid State Drive (SSD), ARW demonstrates significant reductions in both write traffic and overall access latency. Moreover, ARW policies are lightweight, easy to implement, and incur negligible storage and runtime overhead.

In this paper, we propose the Perceptual Shape Decomposition (PSD) to detect fingers for a Kinect-based hand gesture recognition system. The PSD is formulated as a discrete optimization problem by removing all negative minima with minimum cost. Experiments show that our PSD is perceptually relevant and robust against distortion and hand variations, and thus improves the recognition system performance.

Malware phylogeny refers to inferring the evolutionary relationships among instances of a family. It plays an important role in malware forensics. Previous works mainly focused on tree-based model. However, trees cannot represent reticulate events, such as inheriting code fragments from different parents, which are common in variants generation. Therefore, phylogenetic networks as a more accurate and general model have been put forward. In this paper, we propose a novel malware phylogenetic network construction method based on splits graph, taking advantage of the one-to-one correspondence between reticulate events and netted components in splits graph. We evaluate our algorithm on three malware families and two benign families whose ground truth are known and compare with competing algorithms. Experiments demonstrate that our method achieves a higher mean accuracy of 64.8%.

This paper presents the performance modeling, analysis, and simulation of SIP-T (Session Initiation Protocol for Telephones) signaling system in carrier class packet telephony network for NGN (Next Generation Networks). Until recently, fone of the greatest challenges in the migration from existing PSTN (Public Switched Telephone Network) toward NGN is to build a carrier class packet telephony network that preserves the ubiquity, quality, and reliability of PSTN services while allowing the greatest flexibility for use of new packet telephony technology. The SIP-T signaling system defined in IETF (Internet Engineering Task Force) draft is a mechanism that uses SIP (Session Initiation Protocol) to facilitate the interconnection of PSTN with carrier class packet telephony network. Based on IETF, the SIP-T signaling system not only promises scalability, flexibility, and interoperability with PSTN but also provides call control function of MGC (Media Gateway Controller) to set up, tear down, and manage VoIP (Voice over IP) calls in carrier class packet telephony network. In this paper, we derive the buffer size, the mean of queueing delay, and the variance of queueing delay of SIP-T signaling system that are the major performance evaluation parameters for improving QoS (Quality of Service) and system performance of MGC in carrier class packet telephony network focused on toll by-pass or tandem by-pass of PSTN. First, we assume a mathematical model of the M/G/1 queue with non-preemptive priority assignment to represent SIP-T signaling system. Second, we derive the formulas of buffer size, queueing delay, and delay variation for the non-preemptive priority queue by queueing theory respectively. Besides, some numerical examples of buffer size, queueing delay, and delay variation are presented as well. Finally, the theoretical estimates are shown to be in excellent consistence with simulation results.

A novel hybrid latch based flip-flop scheme is introduced in this paper. A pulse generator is eliminated to simplify clock distribution and save power. It also achieves high speed by shortening the critical data path. In addition, it avoids output node glitches which exist in conventional hybrid latch based flip-flops. HSPICE simulation results revealed that the proposed PHLFF performs best among referenced schemes. It can reduce 47.5% power dissipation, 16.5% clock-to-output latency and 56.4% PDP, as compared to conventional HLFF.

An atomistic model for annealing simulation is presented. To well simulate both BED (Boron Enhanced Diffusion) and TED (Transient Enhanced Diffusion), the surface emission model, which describes the emission of point defects from surface during annealing, is implemented. The simulation is carried out for RTA annealing (1000 or 1050) after B implantation. The implantation energy varies from 0.5 keV to 13 keV. Agreements between simulation and SIMS data are achieved. Both BED and TED phenomena are characterized. The Enhancement of diffusion is discussed. The surface emission model is studied by simulation. The results shows that the surface emission has little effect on annealing of B 10 keV implantation while obvious effect on annealing of B 0.5 keV implantation. It indicates that the surface emission is much more necessary to simulate BED than TED.

The potential network architecture of the emerging carrier class VoIP (Voice over IP) technology for NGN (Next Generation Networks) adopts distributed control architecture to take full advantage of scalability, reliability, flexibility, and interoperability. However, the design of distributed control architecture in the carrier class VoIP network is the state-of-the-art in decentralization and distribution of control. Different configurations of system elements, control scheme of inter system elements communications, signaling protocol, functional partitioning, and scheduling of jobs in call control processing may affect the system performance and QoS (Quality of Service) of MGC (Media Gateway Controller) in carrier class VoIP network. Hence, the modeling of distributed control architecture and its performance analysis are essential issues whenever optimum control architecture has to be determined to meet design requirements. Based on these reasons, this paper proposes several potential network architectures and focuses on the performance study of distributed control architecture in carrier class VoIP network. The SIGTRAN-based distributed control architecture model and the MGCP/MEGACO-based distributed control architecture model are presented. Then, we analyze the SIGTRAN-based distributed control architecture model between MGC and SG (Signaling Gateway) using WRR (Weighted Round Robin) and WF2Q (Worst-case Fair Weighted Fair Queueing) scheduling algorithms respectively. And, we analyze the MGCP/MEGACO-based distributed control architecture model between MGC and MG (Media Gateway) using M/G/1 gating service queueing model. Consequently, the results of performance analysis can be used to evaluate whether the performance of distributed control architecture model can meet the requirement of planning and design for carrier class VoIP network deployment.

TCP Friendly Rate Control (TFRC) has been widely used in the Internet multimedia streaming applications. However, performance of traditional TFRC algorithm degrades significantly when deployed over wireless networks. Although numerous TFRC variants have been proposed to improve the performance of TFRC over wireless networks, designing a TFRC algorithm with graceful performance both in throughput and fairness still remains a great challenge. In this paper, a novel TFRC algorithm, named TFRC-FIT, is proposed to improve the performance of TFRC over wireless environments. In the proposed approach, the behavior of multiple TFRC flows is simulated in single connection, while the number of simulated flows is adjusted by the network queuing delay. Through this mechanism, TFRC-FIT can fully utilize the capacity of wireless networks, while maintaining good fairness and TCP friendliness. Both theoretical analysis and extensive experiments over hardware network emulator, Planetlab test bed as well as commercial 3G wireless networks are carried out to characterize and validate the performance of our proposed approach.

In this paper, a new class of low-hit-zone (LHZ) frequency-hopping sequence sets (LHZ FHS sets) is constructed based upon the Cartesian product, and the periodic partial Hamming correlation within its LHZ are studied. Studies have shown that the new LHZ FHS sets are optimal according to the periodic partial Hamming correlation bounds of FHS set, and some known FHS sets are the special cases of this new construction.

Saliency detection for videos has been paid great attention and extensively studied in recent years. However, various visual scene with complicated motions leads to noticeable background noise and non-uniformly highlighting the foreground objects. In this paper, we proposed a video saliency detection model using spatio-temporal cues. In spatial domain, the location of foreground region is utilized as spatial cue to constrain the accumulation of contrast for background regions. In temporal domain, the spatial distribution of motion-similar regions is adopted as temporal cue to further suppress the background noise. Moreover, a backward matching based temporal prediction method is developed to adjust the temporal saliency according to its corresponding prediction from the previous frame, thus enforcing the consistency along time axis. The performance evaluation on several popular benchmark data sets validates that our approach outperforms existing state-of-the-arts.

In quasi-synchronous frequency-hopping multiple access (QS-FHMA) systems, relative delays are allowed to vary in a domain around the origin. Under such condition, the low hit zone (LHZ) frequency-hopping sequence (FHS) set is more propitious than the conventional FHS set to be applied by the systems. In this paper, a construction based on the interleaving techniques of FHS set with LHZ is proposed. Besides the requirement for this constructed LHZ FHS set to get the optimality or the near optimality with respect to the Peng-Fan-Lee bound is also given. It turns out that the constructed LHZ FHS set has new parameters not covered in the literature, thus it does have great significance in practice.

A novel dynamic element matching (DEM) method, called binary-tree random DEM (BTR-DEM), is presented for a Nyquist-rate current-steering digital-to-analog converter (DAC). By increasing or decreasing the number of unit current sources randomly at the same time, the BTR-DEM encoding reduces switch transition glitches. A 5-bit current-steering DAC with the BTR-DEM technique is implemented in a 65-nm CMOS technology. The measured spurious free dynamic range (SFDR) attains 42 dB for a sample rate of 100 MHz and shows little dependence on signal frequency.

This paper presents the performance modeling application of SIP-T (Session Initiation Protocol for Telephones) signaling system based on two-class priority queueing process in carrier class VoIP (Voice over IP) network. The SIP-T signaling system defined in IETF (Internet Engineering Task Force) is a mechanism that uses SIP (Session Initiation Protocol) to facilitate the interconnection of existing PSTN (Public Switched Telephone Network) with carrier class VoIP network. One of the greatest challenges in the migration from PSTN toward NGN (Next Generation Networks) is to build a carrier class VoIP network that preserves the ubiquity, quality, and reliability of PSTN services while allowing the greatest flexibility for use of new VoIP technology. Based on IETF, the SIP-T signaling system not only promises scalability, flexibility, and interoperability with PSTN but also provides call control function of MGC (Media Gateway Controller) to set up, tear down, and manage VoIP calls in carrier class VoIP network. This paper presents the two class priority queueing model, performance analysis, and simulation of SIP-T signaling system in carrier class VoIP network focused on toll by-pass or tandem by-pass of PSTN. In this paper, we analyze the average queueing length, the mean of queueing delay, and the variance of queueing delay of SIP-T signaling system that are the major performance evaluation parameters for improving QoS (Quality of Service) and system performance of MGC in carrier class VoIP network. A mathematical model of the M/G/1 queue with two-class non-preemptive priority assignment is proposed to represent SIP-T signaling system. Then, the formulae of average queueing length, queueing delay, and delay variation for the non-preemptive priority queue are expressed respectively. Several significant numerical examples of average queueing length, queueing delay, and delay variation are presented as well. Finally, the two-class priority queueing model and performance analysis of SIP-T signaling system are shown the accuracy and robustness after the comparison between theoretical estimates and simulation results.

Information security has been seriously threatened by the differential power analysis (DPA). Delay-based dual-rail precharge logic (DDPL) is an effective solution to resist these attacks. However, conventional DDPL convertors have some shortcomings. In this paper, we propose improved convertor pairs based on dynamic logic and a sense amplifier (SA). Compared with the reference CMOS-to-DDPL convertor, our scheme could save 69% power consumption. As to the comparison of DDPL-to-CMOS convertor, the speed and power performances could be improved by 39% and 54%, respectively.

This work reports a novel power-rail electrostatic discharge (ESD) clamp circuit with parasitic bipolar-junction-transistor (BJT) and channel parallel shunt paths. The parallel shunt paths are formed by delivering a tiny ratio of drain voltage to the gate terminal of the clamp device in ESD events. Under such a mechanism, the proposed circuit achieves enhanced robustness over those of both gate-grounded NMOS (ggNMOS) and the referenced gate-coupled NMOS (gcNMOS). Besides, the proposed circuit also achieves improved fast power-up immunity over that of the referenced gcNMOS. All investigated designs are fabricated in a 65-nm CMOS process. Transmission-line-pulsing (TLP) and human-body-model (HBM) test results have both confirmed the performance enhancements of the proposed circuit. Finally, the validity of the achieved performance enhancements on other trigger circuits is essentially revealed in this work.

We propose a current mode sense amplifier that uses a current-mirror to increase the bitline sensing current, which dominates the sensing speed. A comparison of the sensing delay shows that the proposed sense amplifier can provide about 12.6∼15.4% improvement depending on different bitline loads in sensing speed over original WTA scheme.

Side channel attacks (SCAs) on security devices have become a major concern for system security. Existing SCA countermeasures are costly in terms of area and power consumption. This paper presents a novel differential power analysis (DPA) countermeasure referred to as short-time three-phase single-rail precharge logic (STSPL). The proposed logic is based on a single-rail three-phase operation scheme providing effective DPA-resistance with low cost. In the scheme, a controller is inserted to discharge logic gates by reusing evaluation paths to achieve more balanced power consumption. This reduces the latency between different phases, increasing the difficult of the adversary to conduct DPA, compared with the state-of-the-art DPA-resistance logics. To verify the chip's power consumption in practice, a 4-bit ripple carry adder and a 4-bit inverter of AES-SBOX were implemented. The testing and simulation results of DPA attacks prove the security and efficiency of the proposed logic.

Adaptive multilooking is a critical processing step in multi-temporal interferometric synthetic aperture radar (InSAR) measurement, especially in small temporal baseline subsets. Various amplitude-based adaptive multilook approaches have been proposed for the improvement of interferometric processing. However, the phase signal, which is fundamental in interferometric systems, is typically ignored in these methods. To fully exploit the information in complex SAR images, a nonlocal adaptive multilooking is proposed based on complex covariance matrix in this work. The complex signal is here exploited for the similiarity measurement between two pixels. Given the complexity of objects in SAR images, structure feature detection is introduced to adaptively estimate covariance matrix. The effectiveness and reliability of the proposed approach are demonstrated with experiments both on simulated and real data.