In this paper we propose a new timing optimization technique for multi-level networks by restructuring multiple nodes simultaneously. Multi-output subcircuits on critical paths are extracted and resynthesized so that the delays of the paths are reduced. The complete design space of the subcircuits is captured by Boolean relations, which allow us to perform more powerful resynthesis than previous approaches using don't cares. Experimental results are reported to show the effectiveness of the proposed technique.

Boolean unification is an algorithm to obtain the general solution of a given Boolean equation. Since a general solution provides a way to represent a complete don't care set, Boolean unification can be a powerful technique when applied to logic synthesis. In this paper we present various applications of Boolean unification to combinational logic synthesis. Three topics of combinational logic synthesis: redesign, multi-level logic minimization and minimization of Boolean relations are discussed. All these problems can be uniformly formalized as Boolean equations. Experimental results are also reported.