In order to explore the feasibility of large-scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of the minimum operating voltage (VDD min ) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90 nm CMOS ring oscillators (RO's). The measured average VDD min of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of VDD scaling in large-scale subthreshold logic circuits. The dependence of VDD min on the number of stages is calculated using the subthreshold current model with random threshold voltage (VTH) variations and compared with the measured results, and the tendency of the measurement is confirmed. The effect of adaptive body bias control to compensate purely random VTH variation is also investigated. Such compensation would require impractical inverter-by-inverter adaptive body bias control.

Dependence of within-die delay variations on power supply voltage (VDD) is measured down to 0.4 V. The VDD dependence of the within-die delay variation of manual layout and irregular auto place and route (P&R) layout are compared for the first time. The measured relative delay (=sigma/average) variation difference between the manual layout and the P&R layout decreases from 1.56% to 0.07% with reducing VDD from 1.2 V to 0.4 V, because the random delay variations due to the random transistor variations dominate total delay variations instead of the delay variations due to interconnect length variations at low VDD.