This paper shows a describing method of an image processing software in C for high-level synthesis (HLS) technology considering function chaining to realize an efficient hardware. A sophisticated image processing would be built on the sequence of several primitives represented as sub-functions like the gray scaling, filtering, binarization, thinning, and so on. Conventionally, generic describing methods for each sub-function so that HLS technology can generate an efficient hardware module have been shown. However, few studies have focused on a systematic describing method of the single top function consisting of the sub-functions chained. According to the proposed method, any number of sub-functions can be chained, maintaining the pipeline structure. Thus, the image processing can achieve the near ideal performance of 1 pixel per clock even when the processing chain is long. In addition, implicitly, the deadlock due to the mismatch of the number of pushes and pops on the FIFO connecting the functions is eliminated and the interpolation of the border pixels is done. The case study on a canny edge detection including the chain of some sub-functions demonstrates that our proposal can easily realize the expected hardware mentioned above. The experimental results on ZYNQ FPGA show that our proposal can be converted to the pipelined hardware with moderate size and achieve the performance gain of more than 70 times compared to the software execution. Moreover, the reconstructed C software program following our proposed method shows the small performance degradation of 8% compared with the pure C software through a comparative evaluation preformed on the Cortex A9 embedded processor in ZYNQ FPGA. This fact indicates that a unified image processing library using HLS software which can be executed on CPU or hardware module for HW/SW co-design can be established by using our proposed describing method.

In Cognitive Radio Networks (CRNs), spectrum sensing is performed by secondary (unlicensed) users to utilize transmission opportunities, so-called white spaces or spectrum holes, in the primary (licensed) frequency bands. Secondary users (SUs) perform sensing upon arrival to find an idle channel for transmission as well as during transmission to avoid interfering with primary users (PUs). In practice, spectrum sensing is not perfect and sensing errors including false alarms and misdetections are inevitable. In this paper, we develop a continuous-time Markov chain model to study the effect of false alarms and misdetections of SUs on several performance measures including the collision rate between PUs and SUs, the throughput of SUs and the SU delay in a CRN. Numerical results indicate that sensing errors can have a high impact on the performance measures.

Today's enterprise, data-center, and internet-service-provider networks deploy different types of network devices, including switches, routers, and middleboxes such as network address translation and firewalls. These devices are vertically integrated monolithic systems. Software-defined networking (SDN) and network function virtualization (NFV) are promising technologies for dis-aggregating vertically integrated systems into components by using “softwarization”. Software-defined networking separates the control plane from the data plane of switch and router, while NFV decouples high-layer service functions (SFs) or Network Functions (NFs) implemented in the data plane of a middlebox and enables the innovation of policy implementation by using SF chaining. Even though there have been several survey studies in this area, this area is continuing to grow rapidly. In this paper, we present a recent survey of this area. In particular, we survey research activities in the areas of re-architecting middleboxes, state management, high-performance platforms, service chaining, resource management, and trouble shooting. Efforts in these research areas will enable the development of future virtual-network-function platforms and innovation in service management while maintaining acceptable capital and operational expenditure.

Key predistribution schemes (KPSs) have played an important role in security of wireless sensor networks (WSNs). Due to comprehensive and simple structures, various types of combinatorial designs are used to construct KPSs. In general, compared to random KPSs, combinatorial KPSs have higher local connectivity but lower resilience against a node capture attack. In this paper, we apply two methods based on hash chains on KPSs based on transversal designs (TDs) to improve the resilience and the expressions for the metrics of the resulting schemes are derived.

Let $mathbb{F}_q$ be a finite field of q elements, $R=mathbb{F}_q+umathbb{F}_q$ (u2=0) and D2n= be a dihedral group of order n. Left ideals of the group ring R[D2n] are called left dihedral codes over R of length 2n, and abbreviated as left D2n-codes over R. Let n be a positive factor of qe+1 for some positive integer e. In this paper, any left D2n-code over R is uniquely decomposed into a direct sum of concatenated codes with inner codes Ai and outer codes Ci, where Ai is a cyclic code over R of length n and Ci is a linear code of length 2 over a Galois extension ring of R. More precisely, a generator matrix for each outer code Ci is given. Moreover, a formula to count the number of these codes is obtained, the dual code for each left D2n-code is determined and all self-dual left D2n-codes over R are presented, respectively.

As application hardware designs and implementations in a short term are required, high-level synthesis is more and more essential EDA technique nowadays. In deep-submicron era, interconnection delays are not negligible even in high-level synthesis thus distributed-register and -controller architectures (DR architectures) have been proposed in order to cope with this problem. It is also profitable to take data-bitwidth into account in high-level synthesis. In this paper, we propose a bitwidth-aware high-level synthesis algorithm using operation chainings targeting Tiled-DR architectures. Our proposed algorithm optimizes bitwidths of functional units and utilizes the vacant tiles by adding some extra functional units to realize effective operation chainings to generate high performance circuits without increasing the total area. Experimental results show that our proposed algorithm reduces the overall latency by up to 47% compared to the conventional approach without area overheads by eliminating unnecessary bitwidths and adding efficient extra FUs for Tiled-DR architectures.

The heart of Network Functions Virtualization (NFV) is both the softwarization of existing network middleboxes as Virtual Network Functions (VNFs) and the Service Function Chaining (SFC), also known as Service Chaining of them. Most existing VNFs are realized as VM-based general purpose appliances and shared by multiple user VMs. However, the cover range of VNF can be extended to directly reinforce network functionality of user VMs by introducing VM-specific VNFs. In this study, we propose micro-VNFs (µVNFs) and a VM-specific service chaining framework (vNFChain). Micro-VNFs are VM-specific lightweight VNFs that directly attach to a user VM, and can support not only traditional L2-L4 protocols but also stateful custom L7 protocols. The vNFChain framework constructs local service chains of µVNFs and transparently attaches the chain to the VM. Importantly, our framework achieves zero touch configuration for user VMs as well as no modification for existing system environments, such as virtual switch, hypervisor, and OS. In this paper, we describe architectural design and implementation of the framework. In addition, we evaluate the proposed approach in terms of throughput and CPU usage by comparing it with a DPDK-enabled VM-based µVNF model.

We developed a system called DELTA that supports the students' use of backward chaining (BC) to prove the congruence of two triangles. DELTA is designed as an interactive learning environment and supports the use of BC by providing hints and a function to automatically check the proofs inputted by the students. DELTA also has coloring, marking, and highlighting functions to support students' attempts to prove the congruence of two triangles. We evaluated the efficacy of DELTA with 36 students in the second grade of a junior high school in Japan. We found that (1) the mean number of problems, which the experimental group (EG) completely solved, was statistically higher than that of the control group on the post-test; (2) the EG effectively used the BC strategy to solve problems; and (3) the students' attempt to use both the forward chaining strategy and the BC strategy led to solving the problems completely.

This paper describes, for the first time, an experimental study on the layout design considerations of GaAs HBT MMIC switchable-amplifier-chain-based power amplifiers (SWPAs) for CDMA handsets. The transient response of the quiescent current and output power (Pout) in GaAs HBT power amplifiers that consist of a main chain and a sub-chain is often affected by a thermal coupling between power stages and their bias circuits in the same chain or a thermal coupling between power stages and/or their bias circuits in different chains. In particular, excessively strong thermal coupling inside the MMIC SWPA causes failure in 3GPP-compliant inner loop power control tests. An experimental study reveals that both the preheating in the main/sub-chains and appropriate thermal coupling inside the main chain are very effective in reducing the turn-on delay for the two-parallel-amplifier-chain topology; for example, i) the sub-power stage is arranged near the main power stage, ii) the sub-driver stage is placed near the main driver stage and iii) the main driver bias circuit is placed near the main power stage and the sub-power stage. The SWPA operating in Band 9 (1749.9 to 1784.9 MHz), which was designed and fabricated from the foregoing considerations, shows a remarkable improvement in the Pout turn-on delay: a reduced power level error of 0.74 dB from turn-off to turn-on in the sub-amplifier chain and a reduced power level error of over 0.30 dB from turn-off to turn-on in the main amplifier chain. The main RF power measurements conducted with a 3.4-V supply voltage and a Band 9 WCDMA HSDPA modulated signal are as follows. The SWPA delivers a Pout of 28.5 dBm, a power gain (Gp) of 28 dB, and a PAE of 39% while restricting the ACLR1 to less than -40 dBc in the main amplifier chain. In the sub-amplifier chain, 17 dBm of Pout, 23.5 dB of Gp, and 27% of PAE are obtained at the same ACLR1 level.

Service chaining (SC) is a method for realizing a service by transferring flows among several service functions (SFs) that process packets. A route among SFs is called a service path (SP). Service chaining is being developed to reduce costs, increase flexibility, and shorten time-to-market. SC technologies are expected to be applied to carrier networks so that large communication carriers benefit from them. We assume that SPs process the traffic of services that treat all users in the same way such as an Internet access service for home users. An SP processes flows from several users. We do not assume that each SP is assigned to a user. Because a carrier network accommodates many users, each service will be heavily utilized. Therefore, it is assumed that the amount of traffic of a service is larger than the resource of an SF apparatus. Several SPs are required to process the traffic. SPs are supposed to meet two requirements. One is guaranteeing minimum bandwidth. The other is reducing the number of SF apparatuses, i.e., high resource utilization. Resource utilization depends on the combination of the resource quantities of SF apparatuses. Network operators have to determine the bandwidth of each SP within the range from the minimum bandwidth to the resource quantities of SF apparatuses to maximize resource utilization. Methods for determining the bandwidth of each SP have not been proposed for meeting the two requirements. Therefore, we propose a resource allocation method for this purpose. The proposed method determines the bandwidth of each SP on the basis of the combination of the resource quantities of SF apparatuses for guaranteeing the minimum bandwidth and maximizing resource utilization and allocates necessary resources to each SP. We also evaluate the proposed method and confirm that it can guarantee the minimum bandwidth of SPs and achieve high resource utilization regardless of the combination of the resource quantities of SF apparatuses. Although SF apparatuses are generally produced without considering the combinations of resource quantities of SF apparatuses in SPs, the proposed method can provide more options for selecting SF apparatuses.

This paper is a sequel to [4] in which the system is generalized by including unknown time-varying delays in both states and input. Regarding the controller, the design of adaptive gain is simplified by including only x1 and u whereas full states are used in [4]. Moreover, it is shown that the proposed controller is also applicable to a class of upper triangular nonlinear systems. An example is given for illustration.

In this research, we investigated the reliability of a 1-out-of-2 system with two-stage repair comprising hardware restoration and data reconstruction modes. Hardware restoration is normally independently executed by two modules. In contrast, we assumed that one of the modules could omit data reconstruction by replicating the data from the module during normal operation. In this 1-out-of-2 system, the two modules mutually cooperated in the recovery mode. As a first step, an evaluation model using Markov chains was constructed to derive a reliability measure: “unavailability in steady state.” Numerical examples confirmed that the reliability of the system was improved by the use of two cooperating modules. As the data reconstruction time increased, the gains in terms of system reliability also increased.

Recently in an SDN/NFV-enabled network, a consolidated middlebox is proposed in which middlebox functions required by a network flow are provided at a single machine in a virtualized manner. With the promising advantages such as simplifying network traffic routing and saving resources of switches and machines, consolidated middleboxes are going to replace traditional middleboxes in the near future. However, the location of consolidated middleboxes may affect the performance of an SDN/NFV network significantly. Accordingly, the consolidated middlebox positioning problem in an SDN/NFV-enabled network must be addressed adequately with service chain constraints (a flow must visit a specific type of consolidated middlebox), resource constraints (switch memory and processing power of the machine), and performance requirements (end-to-end delay and bandwidth consumption). In this paper, we propose a novel solution of the consolidated middlebox positioning problem in an SDN/NFV-enabled network based on flow clustering to improve the performance of service chain flows and utilization of a consolidated middlebox. Via extensive simulations, we show that our solution significantly reduces the number of routing rules per switch, the end-to-end delay and bandwidth consumption of service flows while meeting service chain and resource constraints.

Let Fq be a finite field of cardinality q, R=Fq[u]/=Fq+uFq+u2Fq+u3Fq (u4=0) which is a finite chain ring, and n be a positive integer satisfying gcd(q,n)=1. For any $delta,alphain mathbb{F}_{q}^{ imes}$, an explicit representation for all distinct (δ+αu2)-constacyclic codes over R of length n is given, and the dual code for each of these codes is determined. For the case of q=2m and δ=1, all self-dual (1+αu2)-constacyclic codes over R of odd length n are provided.

Fast proliferation of mobile Internet and high-demand mobile applications necessitates the introduction of different priority classes in next-generation cellular networks. This is especially crucial for efficient use of radio resources in the heterogeneous and virtualized network environments. Despite the fact that many analytical tools have been proposed for capacity and radio resource modelling in cellular networks, only a few of them explicitly incorporate priorities among services. We propose a novel analytical model to analyse the performance of a priority-based cellular CDMA system with finite source population. When the cell load is above a certain level, low-priority calls may be blocked to preserve the quality of service of high-priority calls. The proposed model leads to an efficient closed-form solution that enables fast and very accurate calculation of resource occupancy of the CDMA system and call blocking probabilities, for different services and many priority classes. To achieve them, the system is modelled as a continuous-time Markov chain. We evaluate the accuracy of the proposed analytical model by means of computer simulations and find that the introduced approximation errors are negligible.

In RFID-enabled supply chains, it is necessary to protect the contents of EPCs (Electronic Product Code) since an EPC contains sensitive information such as the product code and serial number and could be used for counterfeits. Although many protection schemes have been proposed, no scheme can limit the number of illegal attempts for discovering EPCs or notice whether an attacker exists. In this paper, we propose an illegal interrogation detectable products distribution scheme for RFID-enabled supply chains. The idea is to detect the attacker by forcing him/her to access an authentication server. Our scheme masks EPCs with random sequences. Masked EPCs are written into genuine tags on products while random sequences are placed on an authentication server with an access code. An access code is divided into shares with a secret sharing scheme and they are written into genuine tags. We also write bogus shares into extra off-the-shelf tags that are not attached to any products. Since an attacker who wants to know genuine EPCs may obtain a large number of access code candidates and must try each on the authentication server, the server can detect the attacker.

The recent cyber-attacks utilize various malware as a means of attacks for the attacker's malicious purposes. They are aimed to steal confidential information or seize control over major facilities after infiltrating the network of a target organization. Attackers generally create new malware or many different types of malware by using an automatic malware creation tool which enables remote control over a target system easily and disturbs trace-back of these attacks. The paper proposes a generation method of malware behavior patterns as well as the detection techniques in order to detect the known and even unknown malware efficiently. The behavior patterns of malware are generated with Multiple Sequence Alignment (MSA) of API call sequences of malware. Consequently, we defined these behavior patterns as a “feature-chain” of malware for the analytical purpose. The initial generation of the feature-chain consists of extracting API call sequences with API hooking library, classifying malware samples by the similar behavior, and making the representative sequences from the MSA results. The detection mechanism of numerous malware is performed by measuring similarity between API call sequence of a target process (suspicious executables) and feature-chain of malware. By comparing with other existing methods, we proved the effectiveness of our proposed method based on Longest Common Subsequence (LCS) algorithm. Also we evaluated that our method outperforms other antivirus systems with 2.55 times in detection rate and 1.33 times in accuracy rate for malware detection.

Glial cells include several types of cells such as astrocytes, and oligodendrocytes apart from the neurons in the brain. In particular, astrocytes are known to be important in higher brain function and are therefore sometimes simply called glial cells. An astrocyte can transmit signals to other astrocytes and neurons using ion concentrations. Thus, we expect that the functions of an astrocyte can be applied to an artificial neural network. In this study, we propose a multi-layer perceptron (MLP) with a pulse glial chain. The proposed MLP contains glia (astrocytes) in a hidden layer. The glia are connected to neurons and are excited by the outputs of the neurons. The excited glia generate pulses that affect the excitation thresholds of the neurons and their neighboring glia. The glial network provides a type of positional relationship between the neurons in the hidden layer, which can enhance the performance of MLP learning. We confirm through computer simulations that the proposed MLP has better learning performance than a conventional MLP.

In this paper we propose the RF domain beamforming (BF) scheme with a single analog-to-digital/digital-to-analog converters (ADC/DAC) to reduce the power consumption of the chipset for the application to mm-wave WPAN systems and THz communication systems. We also propose the codebook search algorithm for the estimation of the channel state information (CSI) which is a bottleneck to implement the RF BF. Our simulation results show that the deterioration of bit error rate (BER) performance of our proposed design compared to the optimal baseband BF techniques [1], [2] is not significant, while the power consumption and the process time is much reduced.

Camellia is a block cipher jointly developed by Mitsubishi and NTT of Japan. It is designed suitable for both software and hardware implementations. One of the design-for-test techniques using scan chains is called scan-path test, in which testers can observe and control the registers inside the LSI chip directly in order to check if the LSI chip correctly operates or not. Recently, a scan-based side-channel attack is reported which retrieves the secret information from the cryptosystem using scan chains. In this paper, we propose a scan-based attack method on the Camellia cipher using scan signatures. Our proposed method is based on the equivalent transformation of the Camellia algorithm and the possible key candidate reduction in order to retrieve the secret key. Experimental results show that our proposed method sucessfully retrieved its 128-bit secret key using 960 plaintexts even if the scan chain includes the Camellia cipher and other circuits and also sucessfully retrieves its secret key on the SASEBO-GII board, which is a side-channel attack standard evaluation board.