Serial RapidIO (SRIO) is a high-performance interconnection standard for embedded systems. Cyclic Redundancy Check (CRC) provides protection for packet transmissions and impacts the device performances. In this paper, two CRC calculation strategies, based on adjustable slicing parallelization and simplified calculators, are proposed. In the first scheme, the temporary CRC result of the previous cycle (CPre) is considered as a dependent input for the new cycle and is combined with a specific segment of packet data before slicing parallelization. In the second scheme, which can reach a higher maximum working frequency, CPre is considered as an independent input and is separated from the calculation of packet data for further parallelization. Performance comparisons based on ASIC and FPGA implementations are demonstrated to show their effectiveness. Compared with the reference designs, more than 34.8% and 13.9% of average power can be improved by the two proposed schemes at 156.25MHz in 130nm technology, respectively.

Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. Since it is a compute-intensive process which adversely affects performance, hardware acceleration using FPGAs has been tried and satisfactory performance has been achieved. However, recent extended usage of networks and storage systems require various correction capabilities for various CRC standards. Traditional hardware designs based on the LFSR (Linear Feedback Shift Register) tend to have fixed structure without such flexibility. Here, fully-adaptable CRC accelerator based on a table-based algorithm is proposed. The table-based algorithm is a flexible method commonly used in software implementations. It has been rarely implemented with the hardware, since it is believed that the operational speed is not enough. However, by using pipelined structure and efficient use of memory modules in FPGAs, it appeared that the table-based fixed CRC accelerators achieved better performance than traditional implementation. Based on the implementation, fully-adaptable CRC accelerator which eliminate the need for many non-adaptable CRC implementations is proposed. The accelerator has ability to process arbitrary number of input data and generates CRC for any known CRC standard, up to 65 bits of generator polynomial, during run-time. Further, we modify Table generation algorithm in order to decrease its space complexity from O(nm) to O(n). On Xilinx Virtex 6 LX550T board, the fully-adaptable accelerators occupy between 1 to 2% area to produce maximum of 289.8 Gbps at 283.1 MHz if BRAM is deployed, or between 1.6 - 14% of area for 418 Gbps at 408.9 MHz if tables are implemented in logic. Proposed architecture enables further expansion of throughput by increasing a number of input bits M processed at a time.

Three basic ideas for enhancing the performance of extended EPRML (EEPRML) are described in detail. The first is the modification of the EEPRML impulse response in order to minimize the bit error rate of read signals from magnetic recording channels. This modification can improve the signal to noise ratio (S/N) of conventional extended partial response maximum likelihood (EPRML) by approximately 1 dB. The second is the introduction of 16/17 (3;11) maximum transition run code (MTR). This code can completely eliminate error events of more than four consecutive bits from modified EEPRML error events, and reduce the probability of minimum distance error events occurring by one eighth. Finally, dominant error events such as {0e0}, {0ee0}, {0eee0}, and {0e00e0} before 16/17 (3,11) MTR decoding can be corrected by employing cyclic redundancy check code (CRCC) with soft decision decoding. The symbol "e" represents one bit error, namely, "1" to "0" or vice versa and "0" represents a correct bit. Total performance has been evaluated by computer simulations using an isolated waveform similar to actual read signals and additive white Gaussian noise. Consequently, it has been confirmed that modified EEPRML with 16/17 (3;11) MTR code and CRCC can improve the S/N of conventional EPRML by approximately 4 dB at a bit error rate of 10-6.