To reduce mutual coupling of a two-level nested array (TLNA) with an even number of sensors, we propose an improved array configuration that exhibits all the good properties of the prototype optimal configuration under the constraint of a fixed number of sensors N and achieves reduction of mutual coupling. Compared with the prototype optimal TLNA (POTLNA), which inner level and outer level both have N/2 sensors, those of the improved optimal TLNA (IOTLNA) are N/2-1 and N/2+1. It is proved that the physical aperture and uniform degrees of freedom (uDOFs) of IOTLNA are the same as those of POTLNA, and the number of sensor pairs with small separations of IOTLNA is reduced. We also construct an improved optimal second-order super nested array (SNA) by using the IOTLNA as the parent nested array, termed IOTLNA-SNA, which has the same physical aperture and the same uDOFs, as well as the IOTLNA. Numerical simulations demonstrate the better performance of the improved array configurations.

Realizing frequency rectangular characteristics using a planar circuit made of a normal conductor material such as a printed circuit board (PCB) is difficult. The reason is that the corners of the frequency response are rounded by the effect of the low unloaded quality factors of the resonators. Rectangular frequency characteristics are generally realized by a low-noise amplifier (LNA) with flat gain characteristics and a high-order bandpass filter (BPF) with resonators having high unloaded quality factors. Here, we use an LNA and a fourth-order flat passband BPF made of a PCB to realize the desired characteristics. We first calculate the signal and noise powers to confirm any effects from insertion loss caused by the BPF. Next, we explain the design and fabrication of an LNA, since no proper LNAs have been developed for this research. Finally, the rectangular frequency characteristics are shown by a circuit combining the fabricated LNA and the fabricated flat passband BPF. We show that rectangular frequency characteristics can be realized using a flat passband BPF technique.

3D ultrasound imagers require low-noise amplifier (LNA) with much lower power consumption and smaller chip area than conventional 2D imagers because of the huge amount of transducer channels. This paper presents a low-power small-size LNA with a novel current-reuse circuitry for 3D ultrasound imaging systems. The proposed LNA is composed of a differential common source amplifier and a source-follower driver which share the current without using inductors. The LNA was fabricated in a 0.18-μm CMOS process with only 0.0056mm2. The measured results show a gain of 21dB and a bandwidth of 9MHz. The proposed LNA achieves an average noise density of 11.3nV/√Hz, and the 2nd harmonic distortion below -40dBc with 0.1-Vpp input. The supply current is 85μA with a 1.8-V power supply, which is competitive with conventional LNAs by finer CMOS process.

This paper presents a wideband inductorless noise-cancelling balun LNA with two gain modes, low NF, and high-linearity for LTE and intermediate-frequency-band (eg. 3.3-3.6GHz, 4.8-5GHz) 5G applications fabricated in 65nm CMOS. The proposed LNA is bonding tested and exhibits a minimum NF of 2.2dB and maximum IIP3 of -3.5dBm. Taking advantage of an off-chip bias inductor in CG stage and a cross-coupled buffer, the LNA occupies high operation frequency up to 5GHz with remarkable linearity and NF as well as compact area.

A wideband CMOS common-gate low-noise amplifier (LNA) with high linearity is proposed. The linearity is improved by dual cross-coupled feedback technique. A passive cross-coupled feedback removes the second-order harmonic feedback effect to the input-referred third-order intercept point (IIP3), which is known as one of the limitations for linearity enhancement using feedback. An active cross-coupled feedback, constituted by a voltage combiner and a feedback capacitor is employed to enhance loop gain, and acquire further linearity improvement. An enhanced LC-match input network and forward isolation of active cross-coupled feedback enable the proposed LNA with wideband input matching and flat gain performance. Fabricated in a 0.13 µm RF CMOS process, the LNA achieves a flat voltage gain of 13 dB, an NF of 2.6∼3.8 dB, and an IIP3 of 3.6∼4.9 dBm over a 3 dB bandwidth of 0.1∼1.3 GHz. It consumes only 3.2 mA from a 1.2 V supply and occupies an area of 480×418 um2. In contrast to those of reported wideband LNAs, the proposed LNA has the merit of low power consumption and high linearity.

A LNA, an RF front-end and a 6th–order complex BPF for reconfigurable low-IF receivers are demonstrated in this work. Due to the noise cancellation, the two-stage LNA presents a low NF of 2.8 to 3.3 dB from 0.8 to 6 GHz. Moreover, the LNA delivers two kinds of gain curves with IIP3 of -2.6 dBm by employing the capacitive degeneration and the resistive gain-curve shaping in the second stage. The flicker noise corner frequency of the down-converter has been considered and the measured fC of the RF front-end is 200 kHz. The RF front-end also provides two kinds of gain curves. For the low-frequency mode, the conversion gain is 28.831.1 dB from 800 MHz to 2.4 GHz. For the high-frequency mode, the conversion gain is 26.827.4 dB from 3 to 5 GHz. The complex BPF is realized with gm-C LPFs by shifting the low-pass frequency response. With variable transconductances and capacitors, a fixed ratio of the centre frequency to the bandwidth (2) is achieved by varying the bandwidth and the centre frequency of the LPF simultaneously. The complex BPF has a variable bandwidth from 200 kHz to 6.4 MHz while achieving an image rejection of 44 dB.

In this paper, a capacitive-cross-coupling common-gate (CCC-CG) LNA using capacitive feedback is proposed to improve the noise figure (NF). In the conventional CCC-CG LNA, the transconductance gm is determined by the input-matching condition while a lager gm is required to improve NF. gm of the proposed LNA can be increased and NF can be improved by using the added capacitive feedback. The analytical calculation shows that the proposed LNA can perform better than the conventional CCC-CG LNA. In the measurement results using a 0.18-µm CMOS technology, the gain is 10.4–13.4 dB, NF is 2.7–2.9 dB at 0.8–1.8 GHz, and IIP3 is -7 dBm at 0.8 GHz. The power consumption is 6.5 mW with a 1.8-V supply.

A 6–10-GHz broadband low noise amplifier (LNA) and transmitting amplifier (TA) for direct sequence ultra-wideband (DS-UWB) are presented. The LNA and TA are fabricated with the 0.18-µm 1P6M standard CMOS process. The CMOS LNA and TA are checked by on-wafer measurement with the DC supply voltage of 1.5 V. From 6–10 GHz, the broadband LNA exhibits a noise figure of 5.3–6.2 dB, a gain of 11–13.8 dB, a P1 dB of -15.7 - -10.8 dBm, a IIP3 of -5.5 - -1 dBm, a DC power consumption of 12 mW, and an input/output return loss higher than 11/12 dB, respectively. From 6–10 GHz, the broadband TA exhibits a gain of 7.6–10.5 dB, a OP1 dB of 2.8–6.1 dBm, a OIP3 of 12.3–15.1 dBm, and a PAE of 8.8–17.6% @ OP1 dB, and a η of 9.7–21.1% @ OP1 dB, and an input/output return loss higher than 6.8/3.2 dB, respectively.

In this paper a third-order inter-modulation cancellation technique using Pre-Post-Distortion is proposed to design a wideband high linear low-power LNA in deep submicron. The IM3 cancellation is achieved by post-distorting signal inversely after it is pre- distorted in the input trans-conductance stage during amplification process. The operating frequency range of the LNA is 800 MHz–5 GHz. The proposed technique increases input-referred third-order intercept point (IIP3) and input 1 dB Compression point (P-1 dB) to 12–25 dBm and -1.18 dBm, respectively. Post layout simulation results show a noise figure (NF) of 4.1–4.5 dB, gain of 13.7–13.9 dB and S11 lower than -13 dB while consumes 8 mA from 1.2 V supply. The LNA is designed in a 65 nm standard CMOS technology. The layout schematic shows that the LNA occupies 0.150.11 mm2 of silicon area.

An analog controlled Variable Gain LNA (VGLNA) with tunable operating frequency bands is reported. The analog control circuit for the continuous gain variation is proposed as a low voltage version. The fabricated LNA based on 0.18 µm CMOS shows a gain range of 15-12 dB (27 dB gain control), a noise figure (NF) of 2 dB, and an IIP3 of -10 dBm while 5 mA is drawn from a 1.2 V supply over the frequency range of 470880 MHz.

This paper presents the design of a wideband low noise amplifier (LNA) for the 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) standard. The proposed LNA uses a common gate topology with a noise cancellation technique for wideband (0.7 to 2.7 GHz) and low noise operation. The capacitive cross coupling technique is adopted for the common gate amplifier. Consequently input matching is achieved with lower transconductance, thereby reducing the power consumption and noise contribution. The LNA is designed in a 0.18 µm process and the simulations show lower than -10 dB input return loss (S11), and 2.42.6 dB noise figure (NF) over the entire operating band (0.72.7 GHz) while drawing 9 mA from a 1.8 V supply.

A low voltage operational active inductor circuit is attractive for spiral-inductor-less LNA because of realizing high gain and low voltage operation simultaneously. In this paper, a simply structured low-voltage operational active inductor to enhance the amplifier gain is introduced and analyzed. This active inductor, which utilizes a transistor load operated in the triode region and a source follower, features a small DC voltage drop suitable for low voltage LNAs. An LNA using the active inductor load was designed with an input matching circuit using 90 nm CMOS technology. The LNA tuned to 2.4 GHz operation has 19.5 dB of the internal gain. In addition, the frequency characteristics are easily varied by changing the capacitance value in the active inductor circuit. The core circuit occupies only 0.0026 mm2 and consumes 2.8 mW with 1.2 V supply voltage.

E-band low-noise amplifier (LNA) monolithic millimeter-wave integrated circuits (MMICs) were developed using pseudomorphic In0.75Ga0.25As/In0.52Al0.48As high electron mobility transistors (HEMTs) with a gate length of 50 nm. The nanogate HEMTs demonstrated a maximum oscillation frequency (fmax) of 550 GHz and a current-gain cutoff frequency (fT) of 450 GHz at room temperature, which is first experimental demonstration that fmax as high as 550 GHz are achievable with the improved one-step-recessed gate procedure. Furthermore, using a three-stage LNA-MMIC with 50-nm-gate InGaAs/InAlAs HEMTs, we achieved a minimum noise figure of 2.3 dB with an associated gain of 20.6 dB at 79 GHz.

Previously reported wideband CMOS low-noise amplifiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage. We present a transformer noise-canceling wideband CMOS LNA based on a common-gate topology. The transformer, composed of the input and shunt-peaking inductors, partly cancels the noise originating from the common-gate transistor and load resistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA designed for ultra-wideband (UWB) applications is implemented in a 90 nm digital CMOS process. It occupies 0.12 mm2 and achieves |S11|<-10 dB, NF<4.4 dB, and |S21|>9.3 dB across 3.1-10.6 GHz with a power consumption of 2.5 mW from a 1.0 V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.

A high performance highly integrated sub-GHz wideband differential low-noise amplifier (LNA) for terrestrial and cable digital TV tuner applications is realized in 0.18 µm CMOS technology. A noise-canceling topology using a feed-forward current reuse common-source stage is presented to obtain low noise characteristics and high gain while achieving good wideband input matching within 48-860 MHz. In addition, linearization methods are appropriately utilized to improve the linearity. The implemented LNA achieves a power gain of 20.9 dB, a minimum noise figure of 2.8 dB, and an OIP3 of 24.2 dBm. The chip consumes 32 mA of current at 1.8 V power supply and the core die size is 0.21 mm2.

A fully integrated CMOS wideband Low Noise Amplifier (LNA) operating over 2.3-7 GHz is designed and fabricated using a 0.18 µm CMOS process. The proposed structure is a common source-common source (CS-CS) cascode amplifier with a coupling capacitor. It realizes both low voltage drop at load resistor (Rload) and high gain over 2.3-7 GHz with simultaneous noise and input matching and low power consumption. This paper presents the proposed design technique of a wideband LNA, and verifies its performance by simulation and measurement. This wideband LNA achieves an average gain (S21) of 16.5 (dB), an input return loss (S11) less than -8 dB, a noise figure (NF) of 3.4-6.7 dB, and a third order input interception point (IIP3) of -7.5-3 dBm at 2.3-7 GHz with power consumption of 10.8 mW under 1.8 V VDD.

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65 nm and 130 nm CMOS technologies, respectively.

A 0.5 V transformer folded-cascode CMOS low-noise amplifier (LNA) is presented. The chip area of the LNA was reduced by coupling the internal inductor with the load inductor, and the effects of the magnetic coupling between these inductors were analyzed. The magnetic coupling reduces the resonance frequency of the input matching network, the peak frequency and magnitude of the gain, and the noise contributions from the common-gate stage to the LNA. A partially-coupled transformer with low magnetic coupling has a small effect on the LNA performance. The LNA with this transformer, fabricated in a 90 nm digital CMOS process, achieved an S11 of -14 dB, NF of 3.9 dB, and voltage gain of 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW at a 0.5 V supply. The chip area of the proposed LNA was 25% smaller than that of the conventional folded-cascode LNA.

This paper proposes a novel wide-tunable CMOS low-noise amplifier (LNA) using a variable inductor. The variable inductance can be tuned by shielding the magnetic flux, which uses a metal plate above the inductor. The metal plate can be moved using a MEMS actuator. At the present time, the MEMS actuator has not been implemented yet. In this paper, we present a feasibility study on the proposed LNA using the variable inductor. The proposed LNA uses two variable inductors for input and output impedance matching-tuning. The LNA achieves a power gain (PG) of over 10 dB at a tuning range of 1.6-3.2 GHz.

A wideband InGaP/GaAs HBT MMIC amplifier with a low noise characteristic has been developed as a full-band UWB receiver. The amplifier was designed by applying a scaling law to a driver amplifier in order to decrease power consumption, including a modification for decreasing a noise figure. A triple base structure for a double-emitter HBT was employed to decrease a base resistance and to decrease a noise figure of the amplifier. A fabricated amplifier provided a 3-dB gain roll-off bandwidth from 1.1 GHz to 10.6 GHz with a 14.1 dB peak power gain. The amplifier exhibited a low power consumption of 15.9 mW and a low noise figure of less than 3.7 dB in the full-band of the UWB.