This paper introduces several techniques for achieving RF and analog CMOS circuits for wireless communication systems under ultra-low-voltage supply, such as 0.5 V. Forward body biasing and inverter-based circuit techniques were applied in the design of a feedforward Δ-ΣA/D modulator operating with a 0.5 V supply. Transformer utilization is also presented as an inductor area reduction technique. In addition, application of stochastic resonance to A/D conversion is discussed as a future technology.

We present a low-voltage digitally-controlled oscillator (DCO) with the third-order ΔΣ modulator utilized in the medical implant communication service (MICS) frequency band. An optimized DCO core operating in the subthreshold region is designed, based on the gm/ID methodology. Thermometer coder with the dynamic element matching and ΔΣ modulator are implemented for the frequency tuning. High frequency resolution is achieved by using the ΔΣ modulator. The ΔΣ-modulator-based LC-DCO implemented in a 130-nm CMOS technology has achieved the phase noise of -115.3 dBc/Hz at 200 kHz offset frequency with the tuning range of 382 MHz to 412 MHz for the MICS band. It consumes 700 µW from a 0.7-V supply voltage and has a high frequency resolution of 18 kHz.

We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.

Previously reported wideband CMOS low-noise amplifiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage. We present a transformer noise-canceling wideband CMOS LNA based on a common-gate topology. The transformer, composed of the input and shunt-peaking inductors, partly cancels the noise originating from the common-gate transistor and load resistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA designed for ultra-wideband (UWB) applications is implemented in a 90 nm digital CMOS process. It occupies 0.12 mm2 and achieves |S11|<-10 dB, NF<4.4 dB, and |S21|>9.3 dB across 3.1-10.6 GHz with a power consumption of 2.5 mW from a 1.0 V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.

A new small-signal model for fully depleted silicon-on-insulator (FD-SOI) MOSFETs operating at RF frequencies is presented. The model accounts for the non-quasi-static effect by determining model parameters using a curve fitting procedure to reproduce the frequency response of FD-SOI MOSFETs. The accuracy of the model is validated by comparison of S parameters with measured results in the range from 0.2 GHz to 20 GHz.

A 0.5 V transformer folded-cascode CMOS low-noise amplifier (LNA) is presented. The chip area of the LNA was reduced by coupling the internal inductor with the load inductor, and the effects of the magnetic coupling between these inductors were analyzed. The magnetic coupling reduces the resonance frequency of the input matching network, the peak frequency and magnitude of the gain, and the noise contributions from the common-gate stage to the LNA. A partially-coupled transformer with low magnetic coupling has a small effect on the LNA performance. The LNA with this transformer, fabricated in a 90 nm digital CMOS process, achieved an S11 of -14 dB, NF of 3.9 dB, and voltage gain of 16.8 dB at 4.7 GHz with a power consumption of 1.0 mW at a 0.5 V supply. The chip area of the proposed LNA was 25% smaller than that of the conventional folded-cascode LNA.

We present a multiband LTE SAW-less CMOS transmitter with source-follower-driven passive mixers, envelope-tracked RF-programmable gain amplifiers (RF-PGAs), and Marchand Baluns. A driver stage for passive mixers is realized by a source follower, which enables a quadrature modulator (QMOD) to achieve low noise performance at a 1.2 V supply and contributes to a small-area and low-power transmitter. An envelope-tracking technique is adopted to improve the linearity of RF-PGAs and obtain a better Evolved Universal Terrestrial Radio Access Adjacent Channel Leakage power Ratio (E-UTRA ACLR). The Marchand balun covers more frequency bands than a transformer and is more suitable for multiband operation. The proposed transmitter, which also includes digital-to-analog converters and a phase-locked loop, is implemented in a 65-nm CMOS process. The implemented transmitter achieves E-UTRA ACLR of less than -42 dBc and RX-band noise of less than -158 dBc/Hz in the frequency range of 700 MHz–2.6 GHz. These performances are good enough for multiband LTE and SAW-less operation.

A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm2, consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.