Step-edge Josephson junctions (SEJJs), which are made by YBa2Cu3O7 (YBCO) thin films on MgO (100) substrates with gentle step angle (below 40 degrees) have been successfully fabricated. The step-edge, with several angles on the MgO substrate, were made using photolithography and Ar ion beam etching, and then YBCO films were deposited on the step-edges by pulsed laser deposition method. The relationships between step-angles and I-V characteristics, microwave properties and structure of SEJJs were systematically investigated. Shapiro steps were clearly observed only in step-angle range between 10 and 30 degrees. Intermittence and hysteresis on the I-V characteristics were observed above 30 mA without effect from step-angles.

A polarity-convertible driver is necessary as a basic component of several Josephson random access memories. This driver must be able to inject a current having positive or negative polarity into a load transmission line such as a word or bit line of the RAM. In this paper, we propose a resistor coupled Josephson polarity-convertible driver which is highly sensitive to input signals and has a wide operating margin. The driver consists of several Josephson junctions and several resistors. The input signal is directly injected to the driver through the resistors. The circuit design is discussed on the operating principle of the driver. The driver is fabricated by 1.5 µm Nb technology with Nb/AlOx/Nb Josephson junctions, two layer Nb wirings, an Nb ground plane, Mo resistors, and SiO2 insulators. The Nb/AlOx/Nb Josephson junctions are fabricated using technology refined for sub-micron size junctions. The insulators between wirings are formed using bias sputtering technique to obtain good step coverage. The driver circuit size is 53 µm34 µm. Measurements are carried out at 10 kHz to quasistatically test the polarity-convertible function and the operating margin of the driver. Proper polarity-convertible operation is confirmed for a large operating bias margin of 70% at a fairly small input current of 0.3 mA.

We compare interfaces of Nb/AlOx-Al/Nb and Nb/ZrOx-Zr/Nb junctions using secondary ion mass spectroscopy and cross-sectional transmission electron microscopy. We have clarified that an interface of the Nb/AlOx-Al/Nb junction is drastically different from that of the Nb/ZrOxZr/Nb junction. An adsorbed water vapor layer plays an important role in suppressing grain boundary diffusion between Nb and Al at the interface of the Nb/AlOxAl/Nb junction. In depositing Nb and Al at low power and cooling the substrate, it is important to control the formation of the adsorbed water vapor layer for fabricating Nb/AlOx-Al/Nb junctions exhibiting excellent current-voltage characteristics.

We have fabricated Nb/AlOx/Nb Josephson tunnel junctions by a sputtering apparatus with a load-lock system. This sputtering apparatus had the sub chamber for preparation and the main chamber for sputtering. The substrate temperature was confirmed to be kept less than 85 during Nb sputtering at the deposition rate of 1.18 nm/s for 7 minutes. The junctions that had 50µm50 µm area successfully showed the Vm value (the product of the critical current and the subgap resistance at 2 mV) as high as 50 mV at the current density of 100 A/cm2.

We have systematically grown and characterized (Bi, Pb)2Sr2CaCu2Oy (BPSCCO) single crystals, and investigated the tunneling properties and the intrinsic Josephson effects of the single crystals as a function of the nominal composition of Pb, x. It was observed that Pb atoms (ions) were monotonically substituted for Bi atoms (ions) in the (Bi, Pb)-O layers of the crystals with increasing x in a region of 0x0.5, while the modulation structure was maintained in a range of 0x0.3, but disappeared in x0.3, accompanying the decrease of c-lattice parameter and Tc. Moreover, it was found that the energy gaps Δ of BPSCCO depend hardly on x for x0.5, which are about 24 meV, so that the Pb-induced electronic change in the (Bi, Pb)-O layer do not perturb the electronic states in this superconducting system. And it was confirmed that the currentvoltage characteristics of the BPSCCO single crystals had multiple resistive branches corresponding to a series array of several hundreds Josephson junctions, and showed Shapiro steps and zero-crossing steps with the voltage separation of the order of mV resulting from the phase locking of about a hundred Josephson junctions among them under microwave irradiation. The estimated number of junctions gave the concept that the intrinsic Josephson junctions consist of the superconducting block layers and the insulating layers in the BPSCCO single crystals.

Fabrication of all-epitaxial high-Tc SIS tunnel junctions requires an atomically flat superconducting thin film to be grown and a proper insulating material to be selected. First, we study the initial growth mode of YBCO thin films and show that reducing the growth rate results in a very smooth surface. Second, perovskite-related compound oxides, PrGaO3 and NdGaO3, which have a small lattice mismatch with YBCO and good wetability, are shown to be promising insulating materials for all-epitaxial SIS tunnel junctions. We believe that these concepts will be useful in the development of all-epitaxial high-Tc SIS tunnel junctions with good electrical properties.

A new built-in drive circuit for superconducting Josephson LSI circuits has been designed and fabricated in a ceramic multichip module. The drive circuit consists of an impedance matching circuit and a DC bias current feeding circuit to supply a two-phase power current to Josephson chips at a microwave frequency. The impedance matching circuit was designed based on a quarter wavelength stripline. A balanced stripline configuration was introduced to reduce the fluctuation of ground potential. Tungsten layers were used to make the drive circuit in a multilayer ceramic substrate of the multichip module. Whole circuit was successfully packed in a volume of 76 mm38 mm1.7 mm. The gain of microwave current were 20 dB around 1.2 GHz and 23 dB around 3.6 GHz, which were in good agreement with the simulated current gain.

The linear array processor architecture is an important class of interconnection structures that are suitable for VLSI. In this paper we study the problem of mapping a task tree onto a linear array to minimize the total execution time. First, an optimization algorithm is presented for a message scheduling probrem which occurs in the task tree mapping problem. Next, we give a heuristic algorithm for the task tree mapping problem. The algorithm partitions the node set of a task tree into clusters and maps these clusters onto processors. Simulation experiments showed that the proposed algorithm is much more efficient than a conventional algorithm.

This paper studies the problem of embedding a graph into a book with nodes on a line along the spine of the book and edges on the pages in such a way that no edge crosses another. Atneosen as well as Bernhart and Kainen has shown that every graph can be embedded into a 3-page book when each edge can be embedded in more than one page. The time complexity of Bernhart and Kainen's method is Ω(ν(G)), where ν(G) is the crossing number of a graph G. A new 0(mn) algorithm is derived in this paper for embedding a graph G=(V, E), where m=│E│ and n= │V│ . The number of points at which edges cross over the spine in embedding a complete graph into a 3-page book is also investigated.

This letter discusses a behavior of solitons in a Josephson junction transmission line which is described by a perturbed sine-Gordon equation. It is shown that a soliton wave leads a quasi-periodic break down route to chaos in a Josephson transmission line. This route show phase locking, quasi-periodic state, chaos and hyper chaos, and these phenomena are examined by using Poincar sections, circle map, rotation number, and so on.

We have fabricated bi-epitaxial grain boundary junctions in YBa2Cu3O7δ (YBCO) thin films by using SrTiO3 (STO) seed layers on MgO(100) substrate. YBCO film growing over the STO seed layer has a different in-plane orientation from YBCO film without the seed layer, so artificial grain boundaries were created at the edge of the seed layer. The fabricated junctions have high Tc (up to 80 K), and constant-voltage current steps are observed in response to 12.1 GHz microwave radiation. Moreover, some of the junctions show characteristic current-voltage curves comprising not only an usual Josephson-like characteristic but also a low critical current due to the flux creep. This suggests that the two characteristic parts are likely to be connected in series at the junction region.

In this paper, we propose an algorithm of O(|V|min{k,|V|,|A|}|A|) time complexity for finding all k-edge-connected components of a given digraph D=(V,A) and a positive integer k. When D is symmetric, incorporating a preprocessing reduces this time complexity to O(|A|+|V|2+|V|min{k,|V|}min{k|V|,|A|}), which is at most O(|A|+k2|V|2).

The subject of the paper is to propose an O(|V|+|E|) algorithm for the 3-edge-connectivity augmentation problem (UW-3-ECA) defined by "Given an undirected graph G0=(V,E), find an edge set E of minimum cardinality such that the graph (V,EE ) (denoted as G0+E ) is 3-edge-connected, where each edge of E connects distinct vertices of V." Such a set E is called a solution to the problem. Let UW-3-ECA(S) (UW-3-ECA(M), respectively) denote UW-3-ECA in which G0+E is required to be simple (G0+E may have multiple edges). Note that we can assume that G0 is simple in UW-3-ECA(S). UW-3-ECA(M) is divided into two subproblems (1) and (2) as follows: (1) finding all k-edge-connected components of a given graph for every k3, and (2) determining a minimum set of edges whose addition to G0 result in a 3-edge-connected graph. Concerning the subproblem (1), we use an O(|V|+|E|) algorithm that has already been existing. The paper proposes an O(|V|+|E|) algorithm for the subproblem (2). Combining these algorithms makes an O(|V|+|E|) algorithm for finding a solution to UW-3-ECA(M). Furthermore, it is shown that a solution E to UW-3-ECA(M) is also a solution to UW-3-ECA(S) if |V|4, partly solving an open problem UW-k-ECA(S) that is a generalization of UW-3-ECA(S).

This paper deals with the theory and design method of an efficient radix-4 divider using carry-propagation-free adders based on redundant binary {-1,0,+1} representation. The usual method of normalizing the divisor in the range [1/2,1) eliminates the advantages of using a higher radix than two, bacause many digits of the partial remainder are required to select the quotient digits. In the radix-4 case, it is shown that it is possible to select the quotient digits to refer to only the four (in the usual normalizing method it is seven) most significant digits of the partial remainder, by scaling the divisor in the range [12/8,13/8). This leads to radix-4 dividers more effective than radix-2 ones. We use the hyperstring graph representation proposed in Ref.(18) for redundant binary adders.

A vertex-capacitated network is a graph whose edges and vertices have infinite positive capacities and finite positive capacities, respectively. Such a network is a model of a communication system in which capacities of links are much larger than those of stations. This paper considers a problem of realizing a flow-saturation in an undirected vertex-capacitated network by adding the least number of edges. By defining a set of influenced vertex pairs by adding edges, we show the follwing results.(1) It suffices to add the least number of edges to unsaturated vertex pairs for realizing flow-saturation.(2) An associated graph of a flow-unsaturated network defined in this paper gives us a sufficient condition that flow-saturation is realized by adding a single edge.

We discuss fault tolerance of an information disseminating scheme, t-disseminate on a network with N processors, where each processor can send a message to t directions at each round. When N is a power of t+1 and at most tlogt+1N-1 (at most t) processors and/or edges have hailed, logt+1N+(f1)/t rounds (logt+1N+2 rounds) suffice for broadcasting information to all destinations from any source by t-disseminate. For a arbitrary N, logt+1N2f/t1 rounds (logt+1N+2 rounds) suffice for broadcasting information to all destinations from any source by t-disseminate if at most t(logt+1N1)/2 (at most t/2) processors and/or edges have failed.

This paper describes a new method for verifying designs at the RTL with respect to their specifications at the functional level. The base of the verification method shown here is the translation of the specification and design representations to graph models, where the descriptions common to both representations have a symbolic representation. These symbol labeled graphs are then simplified and, by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The first regular expression in each pair represents the flow of control and the second one the flow of data between the corresponding nodes. The process of verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding pair in the design.

Sandwich-type Josephson junctions with the structure Bi2Sr2Ca1Cu2Ox/Bi2Sr2Cu1Oy/Bi2Sr2Ca1Cu2Oz (BSCCO/BSCO/BSCCO), have been fabricated and their characterstics determined. The BSCO barrier layer, which is characterized by a crystal structure close to that of the BSCCO electrode layer, is a normal conductor at 4.2 K. Superconductor/normal-conductor/superconductor (S/N/S) type current-voltage characteristics are obtained with these junctions. Distinctive Shapiro steps are observed when they are exposed to microwave radiation. An oscillating behavior of each step in their I-V characteristics are confirmed for increased microwave power. The critical current, Ic, is found to be proportional to (1-T/Tc)2 in the neighborhood of Tc. These results coincide with the ones observed with conventional S/N/S junctions.

Thin-film YBCO Josephson junctions were successfully fabricated by a pulsed excimer laser ablation, and the mixing experiments in the microwave region (820 GHz) were carried out at the temperature of 77 K. The IF output maximum was obtained at the bias voltage midway between the zero and the first Shapiro steps for the fundamental mixing. For the 2nd harmocic mixing, the IF output maximum was obtained at a zero bias voltage, and the conversion efficiency was -14 dB at the microwave frequency of 18 GHz. These results strongly suggest that the fabricated thin-film Josephson junctions work well at the temperature of 77 K as detectors and mixers in the microwave regions (820 GHz).

Location theory on networks is concerned with the problem of selecting the best location in a specified network for facilities. Many studies for the theory have been done. However, few studies treat location problems on networks from the standpoint of measuring the closeness between two vertices by the capacity (maximum flow value) between two vertices. This paper concerns location problems, called covering problems on flow networks. We define two types of covering problems on flow networks. We show that covering problems on undirected flow networks and a covering problem on directed flow networks are solved in polynomial times.