We fabricated ramp-edge junctions with barriers by modifying surface and integrating ground-planes. The fabricated junctions had current-voltage characteristics consistent with the resistive shunted-junction model. We also obtained a 1-sigma spread in the critical current of 7.9% for 100 junctions at 4.2 K. The ground-plane reduced the sheet inductance of a stripline by a factor of 3. The quality of the ground-plane was improved by using an anneal in oxygen atmosphere after fabrication. The sheet inductance of a counter-electrode with a ground-plane was 1.0 pH per square at 4.2 K.

We have fabricated ramp-type Josephson junctions in trilayer structures. A bilayer of YBa2Cu3O7-x (YBCO)/CeO2 was deposited on a SrTiO3 (100) substrate. Then, circle patterns with a diameter of 2 µm were etched on the bilayer surface using standard photolithography process. During the Ar ion milling with an incident angle of 45 degrees to the bilayer surface, the sample was rotated. This process led to upside-down conical formations. After the ramp-edge surface was modified, another YBCO film was deposited for the top electrode. The junctions showed the I-V characteristics between resistively shunted junction and flux-flow types.

We have fabricated a novel type of intrinsic Josephson junctions with superconducting Bi2Sr2CaCu2O8+y (Bi-2212)/YBa2Cu3O7-x(YBCO) bilayer thin films deposited on MgO(100) substrates. We used the 4th harmonics of a Nd:YAG pulsed laser ablation. Furthermore, we studied the transport properties of a 25 µm 25 µm Bi-2212/YBCO mesa-type junction. The zero resistance temperature was around 50 K. The current-voltage characteristics showed flux-flow-like behavior and a supercurrent of about 2 mA at 4.2 K. Shapiro steps were observed when microwave was irradiated to the mesa junction. These Shapiro steps are attributed to the Josephson junction formed at the interface between the Bi-2212 and YBCO layers in the mesa structure and not to the intrinsic Josephson junctions in the Bi-2212 layer or the micro-grains within the films.

We report some leading research on superconducting devices in Taiwan. Research includes thin films, Josephson junctions, junction arrays and resonators etc. In device physics characteristics of Josephson junctions, junction array, and SQUIDs are reported. Applications of SQUIDs include: (1) studies of brain activities (magnetoencenphalogram) using multichannel low Tc SQUIDs system; (2) detection of weak magnetic fields (magnetocardiogragh, etc. ) using high-Tc SQUIDs; (3) nondestructive evaluation (NDE) of deep flaws using high-Tc SQUIDs. Research projects in the future in our group are briefly reported.

We present analytical and numerical results on the flux-quantum transitions in a three-junction superconducting quantum interference device (3J-SQUID) controlled by two RF signals. The 3J-SQUID has two superconducting loops, and the RF signals are magnetically coupled to the loops. Flux-quantum transitions in the 3J-SQUID loops can be controlled by utilizing the phase difference of the two RF signals. Under proper conditions, we can obtain a situation where one flux quantum passes through the 3J-SQUID per one cycle of the RF signals without DC current biasing, which results in a zero-crossing step on the current-voltage characteristics. In this paper, we first explain the operation principle by using a quantum state diagram of a 3J-SQUID. Next, we numerically simulate RF-induced transitions of the quantum states. A zero-crossing step on the current-voltage characteristics is demonstrated. We also investigate dependence of zero-crossing steps upon parameters of the 3J-SQUID and RF signals.

In this paper, we investigate self diagnosable systems on multi-processor systems, known as one-step t-diagnosable systems introduced by Preparata et al. Kohda has proposed "highly structured system" to design diagnosable systems such that faulty processors are diagnosed efficiently. On the other hand, it is known that Cayley graphs have been investigated as good models for architectures of large-scale parallel processor systems. We investigate some conditions for Cayley graphs to be topologies for optimal highly structured diagnosable systems, and present several examples of optimal diagnosable systems represented by Cayley graphs.

In screening for primary lung cancer with plain chest radiography, computer-aided diagnosis systems are being developed to reduce chest radiologists' task and the risk of missing positive cases. We evaluated a difference filter that enhances nodule densities in the preprocessing of chest X-ray images. Since ribs often affect detection of pulmonary nodules, we designed an eye-shaped filter to fit the rib shape. Although this filter increased the nodule detection rate, it could not detect nodules near the thoracic wall. The thoracic wall was then outlined by computers with Hough transformation for line detection. On the basis of the outline, the direction of the eye-shaped filter was determined. With this technique, the filter was not affected by considerable changes in the shape of anatomical structures, such as ribs and the thoracic wall, and could detect pulmonary nodules regardless of their location.

In this paper, we give an algorithm for the node-to-set disjoint paths problem in rotator graphs with its evaluation results. The algorithm is based on recursion and it is divided into cases according to the distribution of destination nodes in classes into which all the nodes in a rotator graph are categorized. The sum of the length of paths obtained and the time complexity of the algorithm are estimated and verified by computer simulation.

Although many successful asynchronous control circuit synthesis methods are available, it is still unwieldy to conceive and describe the behaviors of a number of controllers which constitute a control unit of a target system manually. In this paper, an automatic and systematic method to derive an efficient asynchronous control unit from a system specification, a control data flow graph (CDFG), is suggested. In order to acquire an asynchronous control unit of acceptable quality, a new process-oriented method is proposed. In this method, the resulting asynchronous control unit has complete separation of 'execution controllers' and 'execution order controllers' according to the hierarchical decomposition of a given CDFG. This distributive feature leads to a significant improvement in area, performance, implementability and synthesis time for the derived asynchronous control units.

In SDMA, a spatial domain interference canceller applying a multistage processing concept to the MMSE multibeam adaptive array has an attractive feature. Weak power signals strongly interfered can be detected in the succeeded stages after removing other strong power signals which are already detected. This idea can be enhanced to the reference timing estimation required in the MMSE algorithm. In this paper, the spatial domain interference canceller introducing multistage timing estimation is proposed and its performance is evaluated by computer simulations. The results show that the timing estimation performance highly improved.

A parallel program with a fixed degree of parallelism cannot be executed efficiently, or at all, by a parallel computer with a different degree of parallelism. This will cause a problem in the distribution of software applications in the near future when parallel computers with various degrees of parallelism will be widely used. In this paper we propose a way to make the machine code of the programs parallelism-independent, i.e. executable in minimum time on parallel computers with any degree of parallelism. We propose and evaluate three parallelism-independent scheduling algorithms for direct acyclic graphs (DAGs) of tasks with non-uniform execution times. To prove their efficiency, we performed simulations both with random DAGs and DAGs extracted from real applications. We evaluate them in terms of schedule length, computation time and size of the scheduled program. Their results are compared to those of the traditional CP/MISF algorithm which is used separately for each number of processors.

A schedule for a parallel program is said to be 1-fault-secure if a system that uses the schedule can either produce correct output for the program or detect the presence of any faults in a single processor. Although several fault-secure scheduling algorithms have been proposed, they can all only be applied to a class of tree-structured task graphs with a uniform computation cost. Besides, they assume a stringent error model, called the redeemable error model, that considers extremely unlikely cases. In this paper, we first propose two new plausible error models which restrict the manner of error propagation. Then we present three fault-secure scheduling algorithms, one for each of the three models. Unlike previous algorithms, the proposed algorithms can deal with any task graphs with arbitrary computation and communication costs. Through experiments, we evaluate these algorithms and study the impact of the error models on the lengths of fault-secure schedules.

We propose the problem of how to transmit an information-theoretically secure bit using random deals of cards among players in hierarchical groups and a computationally unlimited eavesdropper. A player in the highest group wants to send players in lower groups a secret bit which is secure from the eavesdropper and some other players. We formalize this problem and design protocols for constructing secret key exchange spanning trees on hierarchical groups. For each protocol we give sufficient conditions to successfully construct a secret key exchange spanning tree for the hand sizes of the players and the eavesdropper.

We propose a dynamic assignment method of radio channels using their qualities and data packet sizes. In this method, a high quality channel is assigned for long packets and a low quality channel is assigned for short packets. Assuming a packet transfer method based on PHS (Personal Handy System) procedure, the transfer speed and delay characteristics are investigated by computer simulation and compared with conventional method (i.e. random assignment). Both the transfer speed characteristics and delay performance are improved under light traffic load.

If there exist any two vertices in G whose distance becomes longer when a vertex u is removed, then u is defined as a hinge vertex. Finding the set of hinge vertices in a graph can be used to identify critical nodes in an actual network. A number of studies concerning hinge vertices have been made in recent years. In general, it is known that more efficient sequential or parallel algorithms can be developed by restricting classes of graphs. For instance, Chang et al. presented an O(n+m) time algorithm for finding all hinge vertices of a strongly chordal graph. Ho et al. presented a linear time algorithm for all hinge vertices of a permutation graph. In this paper, we shall propose a parallel algorithm which runs in O(log n) time with O(n) processors on CREW PRAM for finding all hinge vertices of an interval graph.

It is difficult for an adaptive array to reduce interference signals efficiently from received signals when the interference signals and desired signal are closely located. This is a problem for a spatial division multiple access (SDMA) system using the multibeam adaptive array as a multiuser detector. In this paper, we propose a space domain multistage interference canceller (SD-MIC) for the SDMA system. Its performance is evaluated by computer simulations, assuming Japanese personal handy phone system (PHS) uplink environments. The results show remarkable improvement in high spatial correlation situations.

C-axis junction-arrays, with a-b plane sizes of sub-microns to 10 microns, were patterned on Bi2Sr2CaCu2O8+x single crystals with either a mesa or an overlap structure. We measured the current-voltage (I-V) characteristics with microwave irradiation at a few to 100 gigahertz. At a few gigahertz, often observed were chaotic properties. Under irradiation at 100 GHz, we successfully performed harmonic mixings between the 100 GHz signal and up to the 100th harmonic of a local oscillator at about 1 GHz. Given in this paper are discussions on the observation of individual Shapiro steps, and descriptions of the relevant results. Our experimental results show that intrinsic Josephson junctions in layered superconductors can be good candidates for high frequency applications.

We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.

Fabrication technology for Nb integrated circuits has been developed. In developing fabrication technology, the key process steps are the etching to form fine Nb electrodes and the formation of reliable insulation layers. The standard process has been developed focusing on reproducibility and reliability. In the process, conventional reactive ion etching and RF bias-sputter deposition are used. The number of Nb wiring layers is two, and standard deviation (σ) of critical current is 0.9%, 2.3%, and 4.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. The advanced process has also been developed focusing on capability of increasing the integration scale. Electron-cyclotron-resonance plasma etching and mechanical polishing planarization have been developed as advanced process technology. The number of Nb wiring layers is three, and σ is improved to 0.8%, 0.7%, and 1.7% for the junction sizes of 2 µm, 1.4 µm, and 1 µm, respectively. Integration limits are discussed and it is estimated that the maximum number of junctions is in the order of 105 and 107 for the standard and the advanced process, respectively. A large-scale superconducting circuit such as a several M-bit RAM can be realized in the future by using these fabrication technologies.

A variety of mobile data communication services based on cellular phones and the PHS (Personal Handyphone System) have recently been developed and used widely. The maximum transmission rate in public mobile data communication services is currently limited to 64 kbit/s, but higher transmission rate will be needed in order to meet the requirements of mobile multimedia applications. We have therefore developed 384 kbit/s-PHS experimental system that uses the 64 kbit/s PHS data communication protocol (PIAFS) and the PPP Multilink protocol. This paper presents the implementation and performance evaluation of the 384 kbit/s-PHS experimental system. Throughtput performance of the system is evaluated using FTP under various radio propagation environments.