In order to investigate the jitter characteristics of PLLs for practical applications, we have developed a computer simulation program of PLL, which can deal with arbitrary patterns both of data and jitters, as well as a conceivable nonlinearity of the circuit performance. We used a time-domain method, namely, we solved the state equation of a charge pump type PLL with a constant time step. The jitter transfer characteristics of a conventional PLL were calculated for periodic input data patterns with sinusoidal jitters. The result agreed fairly well with the corresponding experiments. And we have revealed that an ordinary PD (Phase Detector), which detects the phase difference between input and VCO signals at only rising edges, shows the folded jitter transfer characteristics at the half of the equivalent frequency of the input signal. This folded jitter characteristics increases the total jitter for long successive '1' or '0' data patterns, because of their low equivalent sampling frequency, and might increase the jitter even for the random data patterns. Based on simulation results, we devised an improved phase detector for PLL having a low jitter characteristics. And we also applied the simulation to an FDD (Frequency Difference Detector) type fast pull-in PLL which we have proposed recently, and obtained that the jitter of it was smaller than that of a conventional PLL by 25% for PRBS (pseudo random bit sequence) NRZ code.

This paper proposes a self frequency preset (SFP) PLL synthesizer to realize a simple frequency preset PLL synthesizer with temperature-resistant and shorter frequency settling time than the conventional temperature un-compensated phase and frequency preset (PFP) PLL synthesizer. Since the proposed synthesizer employs a simple frequency locked loop (FLL) circuit to preset the output frequency at each frequency hopping period, the synthesizer eliminates the need to store f-V characteristic of the VCO in ROM. The frequency settling time of the proposed synthesizer is theoretically and experimentally analyzed. The theoretical analysis using the realistic f-V characteristic of a IF band VCO show that the frequency settling time of the proposed synthesizer is 130µs shorter than that of the conventional PFP PLL synthesizer at 40MHz hopping in the 200MHz band for all temperatures. Furthermore, the experimental results confirm that the frequency acquisition time of a prototype FLL circuit is accordant with the calculated results. Thus, the proposed SFP PLL synthesizer can achieve faster frequency settling than the conventional PFP PLL synthesizer for all temperatures and its simple configuration allows to be easily implemented with existing CMOS ASIC devices.

This paper proposes a high resolution and fast frequency settling PLL synthesizer for frequency hopping radio communication equipment. The proposed synthesizer enables the carrier frequency to be changed within the duration of a burst signal and yields higher frequency resolution than the reference signal frequency. To reduce frequency settling time without degradation of frequency resolution and phase noise, this paper proposes a new phase and frequency preset (PEP) PLL synthesizer which employs a digital phase accumulator to generate high resolution reference signal. Experimental results show that the settling time of a prototype synthesizer is less than 300µs while spurious signals are suppressed by more than 55 dB. In comparison with conventional PLL synthesizers, the frequency settling time is reduced by 80%. Furthermore, the higher frequency resolution than the reference signal is successfully demonstrated. Therefore, the proposed PFP PLL synthesizer with the digital reference signal can achieve the output signal with high frequency resolution less than 1Hz.

A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.