Influence of the resistance of the ground line in D/A converter has been analyzed. The resistance produces a significant linearity error if a conventional switching sequence is used. The proposed new compensation technique named symmetrical switching reduces the error to 25 %.

A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.

A new approach to implement queues for controlling ATM switch LSI is presented. In many conventional architecture, external FIFOs are provided for each output link and used to manage the address of the buffer in an ATM switch. We reduce the number of FIFOs by using a self-timed queue with a search circuit that finds the earliest entry for each output link. Using this architecture, number of the FIFOs is reduced to 1/N, where N is the switch size. Delay priority and multicasting can be supported without doubling the number of the queues. This new queue can also be utilized as an ATM switch by itself. Evaluation chip was fabricated using 0.5-µm CMOS process technology. Inter-stage transfer speed over 500 MHz and cycle time over 125 MHz was obtained. This performance is enough for a 622-Mbps 1616 ATM Switch.

Superscalar processors improve performance by exploiting instruction-level parallelism (ILP). ILP in a basic block is, however, not sufficient on non-numerical applications for gaining substantial speedup. Instructions across branches are required to be executed in parallel to dramatically improve performance. That is, speculative execution is strongly required. Boosting is a general solution to achieving speculative execution. Boosting labels an instruction to be speculatively executed, and the hardware handles side-effects. This paper describes the efficient implementation of boosting in terms of cost/performance trade-offs. Our policy in implementation is beneficial in code scheduling heuristics, penalties imposed by code duplication to maintain program semantics, and area cost. This paper also describes a branch scheme which minimizes branch penalty. Branch delay causes crucial penalties on the performance of superscalar processors since multiple delay slots exist even in a single delay cycle. Our scheme is the fetching of both sequential and target instructions, and either of them is selected on a branch. No delay cycle can be imposed. This scheme is realized by a combination of static code movement and hardware support. As a result, we reduce branch penalty with small cost. Simulation results show that our ideas are highly effective in improving the performance of a superscalar processor.

A new shared multibuffer architecture for high-speed ATM (Asynchronous Transfer Mode) switch LSIs is described. Multiple buffer memories are located between two crosspoint switches. By controlling the input-side crosspoint switch so as to equalize the utilization rate of each buffer memory, these multiple buffer memories can be recognized as a single large shared buffer memory. High utilization efficiency of buffer memory can thus be achieved, and the cell loss ratio is minimized. By accessing the buffer memories in parallel via crosspoint switches, the time required to access the buffer memories is greatly reduced. This feature enables high-speed operation of the switch. The shared multibuffer architecture was implemented in a switch LSI using 0.8-µm BiCMOS process technology. Experimental results revealed that this chip can operate at more than 125 MHz. Bit-sliced eight switch LSIs operating at 78 MHz construct a 622-Mb/s 88 ATM switching system with a buffer size of 1,024 ATM cells. Power consumption of the switch LSI was 3 W.