A wide-range multiphase delay-locked loop (DLL) using mixed-mode voltage-controlled delay lines (VCDLs) is presented. An edge-triggered duty cycle corrector is introduced to generate output clocks with 50% duty cycle. This DLL using an analog 3-states phase-frequency detector (PFD) and the proposed digital PFD can achieve low jitter operation over a wide frequency range without harmonic locking problems. It has been fabricated in a standard 0.25-µm CMOS technology and occupies a core area of 1 mm2 including the on-chip regulator and loop filter. For reference clocks from 20 MHz to 550 MHz, all the measured rms and peak-to-peak jitters are below 10 ps and 78 ps, respectively.

An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 500.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.