An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications

Jang-Jin NAM; Hong-June PARK

doi:10.1093/ietele/e88-c.4.773

An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications

Jang-Jin NAM, Hong-June PARK

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An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 500.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.

Publication: IEICE TRANSACTIONS on Electronics Vol.E88-C No.4 pp.773-777

Publication Date: 2005/04/01

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DOI: 10.1093/ietele/e88-c.4.773

Type of Manuscript: LETTER

Category: Electronic Circuits

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Jang-Jin NAM, Hong-June PARK, "An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications" in IEICE TRANSACTIONS on Electronics, vol. E88-C, no. 4, pp. 773-777, April 2005, doi: 10.1093/ietele/e88-c.4.773.
Abstract: An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 500.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.4.773/_p

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@ARTICLE{e88-c_4_773,
author={Jang-Jin NAM, Hong-June PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications},
year={2005},
volume={E88-C},
number={4},
pages={773-777},
abstract={An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 500.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.},
keywords={},
doi={10.1093/ietele/e88-c.4.773},
ISSN={},
month={April},}

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TY - JOUR
TI - An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 773
EP - 777
AU - Jang-Jin NAM
AU - Hong-June PARK
PY - 2005
DO - 10.1093/ietele/e88-c.4.773
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2005
AB - An all-digital CMOS duty cycle correction (DCC) circuit with a fixed rising edge was proposed to achieve the wide correction ranges of input duty cycle and PVT variations, the low standby power and the fast recovery from the standby mode for use in multi-phase clock systems. SPICE simulations showed that this DCC adjusts the output duty cycle to 500.7% for the wide range of input duty cycle from 15% to 85% at the input frequency of 1 GHz, within the commercial range of PVT corners. The all-digital implementation and the use of a toggle flip flop at the input stage enabled the wide correction ranges of PVT variations and input duty cycle, respectively.
ER -