This paper presents a design optimization method for a Gm-C active filter via geometric programming (GP). We first describe a GP-compatible model of a cascaded Gm-C filter that forms a biquadratic output transfer function. The bias, gain, bandwidth, and signal-to-noise ratio (SNR) of the Gm-C filter are described in a GP-compatible way. To further enhance the accuracy of the model, two modeling techniques are introduced. The first, a two-step selection method, chooses whether a saturation or subthreshold model should be used for each transistor in the filter to enhance the modeling accuracy. The second, a bisection method, is applied to include non-posynomial inequalities in the filter modeling. The presented filter model is optimized via a GP solver along with proposed modeling techniques. The numerical experiments over wide ranges of design specifications show good agreement between model and simulation results, with the average error for gain, bandwidth, and SNR being less than 9.9%, 4.4%, and 14.6%, respectively.

As CMOS devices scaling down in nowadays integrated circuits, the impact of layout-dependent effects (LDEs) to circuit performances becomes to be significant. This paper mainly focuses on LDE-aware analog circuit synthesis. Our circuit synthesis follows an optimization framework of transistor sizing based on geometric programming (GP) in which analog circuit performances are formulated in terms of monomials and posynomials. Providing GP models for the LDEs such as the shallow trench isolation (STI) stress and the well proximity effect (WPE), we can generate layout constraints related to LDEs during the circuit synthesis. Applying our circuit synthesis to a typical two-stage op-amp, we showed that the resultant circuit, which generated by GP with circuit performance and layout constraints, satisfied all the specifications with the verification of HSPICE simulation based on the BSIM model with LDE options.

MIMO two-way multi-hop networks are considered in which the radio resource is fully reused in all multi-hop links to increase spectrum efficiency while the adjacent interference signals are cancelled by MIMO processing. In addition, the nodes in the multi-hop network optimize their transmit powers to mitigate the remaining overreach interference. Our main contribution in this paper is to investigate an efficient relay placement method with power allocation in such networks. We present two formulations, namely QoS-constrained optimization and SINR balancing, and solve them using a sequential geometric programming method. The proposed algorithm takes advantage of convex optimization to find an efficient configuration. Simulation results show that relay placement has an important impact on the effectiveness of power allocation to mitigate the interference. Particularly, we found that an uniform relay location is optimal only in power-limited scenarios. With optimal relay locations, significant end-to-end rate gain and power consumption reduction are achieved by SINR balancing and QoS-constrained optimization, respectively. Furthermore, the optimal number of hops is investigated in power or interference-limited scenarios.

Recently, a flexible loss recovery scheme, called Active Caching (AC) has been proposed to accomplish a Desired Communication Reliability (DCR) about the whole data packets at a source depending on the various applications. However, since AC does not consider the packet delivery rate of each wireless link on multi-hop forwarding paths, it increases the number of totally transmitted packets to achieve a DCR and thus grows the energy consumption of sensor nodes. Thus, this letter proposes a novel recovery scheme which can minimize the number of totally transmitted packets while satisfying a DCR. By geometric programming, the proposed scheme allocates an optimized one-hop packet transmission rate of each wireless link on the multi-hop forwarding path.

In this letter, coordinated power allocation (PA) is investigated for the downlink of a generalized multi-cluster distributed antenna system (DAS). Motivated by practical applications, we assume only the global large-scale channel state information is known at the transmitter. First, an upper bound (UB) for the ergodic sum capacity of the system is derived and used as a simplified optimization target. Then, a coordinated PA scheme is proposed based on Geometric Programming (GP), which is demonstrated to be nearly optimal by Monte Carlo simulations.

This paper presents an efficient algorithm for incremental buffer insertion and module resizing for a full-placed floorplan. Our algorithm offers a method to use the white space in a given floorplan to resize modules and insert buffers, and at the same time keeps the resultant floorplan as close to the original one as possible. Both the buffer insertion and module resizing are modeled as geometric programming problems, and can be solved extremely efficiently using new developed solution methods. The experimental results suggest that the the wire length difference between the initial floorplan and result are quite small (less than 5%), and the global structure of the initial floorplan are preserved very well.

We present an efficient method to optimize network resource allocations under nonlinear Quality of Service (QoS) constraints. We first propose a suite of generalized proportional allocation schemes that can be obtained by minimizing the information-theoretic function of relative entropy. We then optimize over the allocation parameters, which are usually design variables an engineer can directly vary, either for a particular user or for the worst-case user, under constraints that lower bound the allocated resources for all other users. Despite the nonlinearity in the objective and constraints, we show this suite of resource allocation optimization can be efficiently solved for global optimality through a convex optimization technique called geometric programming. This general method and its extensions are applicable to a wide array of resource allocation problems, including processor sharing, congestion control, admission control, and wireless network power control.

In this paper we describe a method for the automated design of analog circuits. The method simultaneously sizes the different components (transistors, capacitors, etc.) in a pre-defined circuit topology and places them according to a pre-defined slicing tree. The method is based on formulating the circuit physical and electrical behavior in a special convex form. More specifically, we cast the design problem as a geometric program, a special type of convex optimization problem. Therefore, all design constraints are formulated as posynomial inequality or monomial equality constraints. Very efficient numerical algorithms are then used to solve the resulting geometric program and to create the design that meets the desired specifications. The formulation is hierarchical and modular, allowing easy topology re-use and process porting. The synthesis method is fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point, and infeasible specifications are unambiguously detected. After a brief overview of current analog design automation solutions, we describe our method and provide some design examples for op-amps and analog-to-digital converters.