This paper presents a fully integrated 32-MHz relaxation oscillator (ROSC) capable of sub-1-µs start-up time operation for low-power intermittent VLSI systems. The proposed ROSC employs current mode architecture that is different from conventional voltage mode architecture. This enables compact and fast switching speed to be achieved. By designing transistor sizes equally between one in a bias circuit and another in a voltage to current converter, the effect of process variation can be minimized. A prototype chip in a 0.18-µm CMOS demonstrated that the ROSC generates a stable clock frequency of 32.6 MHz within 1-µs start-up time. Measured line regulation and temperature coefficient were ±0.69% and ±0.38%, respectively.

We propose a new fine Doppler frequency estimator using two fast Fourier transform (FFT) samples for pulse Doppler radar that offers highly sensitive detection and a high resolution of velocity. The procedure of fine Doppler frequency estimation is completed through coarse frequency estimation (CFE) and fine frequency estimation (FFE) steps. During the CFE step, the integer part of the Doppler frequency is obtained by processing the FFT, after which, during the FFE step, the fractional part is estimated using the relationship between the FFT peak and its nearest resultant value. Our simulation results show that the proposed estimator has better accuracy than Candan's estimator in terms of bias. The root mean square error (RMSE) of the proposed estimator has more than 1.4 time better accuracy than Candan's estimator under a 1,024-point FFT and a signal-to-noise ratio (SNR) of 10 dB. In addition, when the FFT size is increased from 512 to 2,048, the RMSE characteristics of the proposed estimator improve by more than two-fold.

Digital signal processing requires digital filters with variable frequency characteristics. A variable digital filter (VDF) is a filter whose frequency characteristics can be easily and instantaneously changed. In this paper, we present a design method for variable linear-phase finite impulse response (FIR) filters with multiple variable factors and a reduction method for the number of polynomial coefficients. The obtained filter has a high piecewise attenuation in the stopband. The stopband edge and the position and magnitude of the high piecewise stopband attenuation can be varied by changing some parameters. Variable parameters are normalized in this paper. An optimization methodology known as semidefinite programming (SDP) is used to design the filter. In addition, we present that the proposed VDF can be implemented using the Farrow structure, which suitable for real time signal processing. The usefulness of the proposed filter is demonstrated through examples.

This paper proposes a design method of 2-D variable IIR digital filters with high frequency tuning accuracy. In the proposed method, a parallel complex allpass structure is used as the prototype structure of the 2-D variable digital filters in order to obtain low sensitivity characteristic. Because the proposed 2-D variable digital filter is composed of first-order complex allpass sections connected in parallel, the proposed variable digital filter possesses several advantages such as low sensitivity characteristic in the passband, simple stability monitoring and high parallelism. In order to improve the frequency tuning accuracy of the proposed variable digital filter, each first-order complex allpass section is substituted by a new first-order complex allpass section with low sensitivity characteristic. Moreover, the coefficient sensitivity analysis of a 2-D parallel complex allpass structure is presented. Numerical examples show that the proposed 2-D variable IIR digital filter has high tuning accuracy under the finite coefficient wordlength.

This paper describes an MOS current-mode sample-and-hold (S/H) circuit that potentially operates with a sub-1. 5 V supply voltage, 20 MHz clock frequency, and less than 0. 1% linearity. A newly developed voltage-to-current converter suppresses the voltage change at an input terminal and achieves low-voltage operation with superior linearity. Sample switches are differentially placed at the inputs of a differential amplifier so that the feedthrough errors from switches cancel out. The MOS current-mode S/H circuit is designed and simulated using CMOS 0. 6 µm device parameters. Simulation results indicate that an operation with 20 MHz clock frequency, linearity error of less than 0. 1%, and 1 MHz input from a 1. 5 V power supply is achievable.

A noise cancelling sonar-ranging system based on the adaptive filtering technique, which can automatically adapt itself to the changes in environmental noise-field and improve the passive sonar-ranging/goniometric precision, was introduced by this paper. In the meantime, the software and hardware design principle of the system using high speed VLSI (Very Large Scale Integrated) DSP (Digital Signal Processing) chips, and the practical test results were also presented. In comparison with the traditional ranging system, the system not only enhanced obviously the ranging precision but also possessed some more characteristics such as simple structure, rapid operation, large data-storage volume, easy programming, high reliability and so on.