This paper investigates the design curves of class E amplifier with nonlinear capacitance for any output Q and finite dc-feed inductance. The important results are; 1) the capacitance nonlinearity strongly affects the design parameters for low Q, 2) the value of dc-feed inductance is hardly affected by the capacitance nonlinearity, and 3) the input voltage is an important parameter to design class E amplifier with nonlinear capacitance. By carrying out PSpice simulations, we show that the simulated results agree with the desired ones quantitatively. It is expected that the design curves in this paper are useful guidelines for the design of class E amplifier with nonlinear capacitance.

With increase of clock frequency, on-chip wire inductance starts to play an important role in power/ground distribution analysis, although it has not been considered so far. We perform a case study work that evaluates relation between decoupling capacitance position and noise suppression effect, and we reveal that placing decoupling capacitance close to current load is necessary for noise reduction. We experimentally show that impact of on-chip inductance becomes small when on-chip decoupling capacitance is well placed according to local power consumption. We also examine influences of grid pitch, wire area, and spacing between paired power and ground wires on power supply noise. When effect of on-chip inductance on power/ground noise is significant, minification of grid pitch is more efficient than increase in wire area, and small spacing reduces power noise as we expected.

The scaled down feature size and the increased frequency of today's deep sub-micron region call for fundamental changes in driver-load models. To be more specific, new driver-load models need to take into consideration the nonlinear behavior of the drivers, the inductance effects of the loads, and the slew rates of the output waveforms. Current driver-load models use the conventional single Ceff (one-ramp) approach and treat the interconnect load as lumped RC networks. Neither the nonlinear property nor the inductance effects were considered. The accuracy of these existing models is therefore questionable. This paper introduces a new multi-ramp driver model that represents the interconnect load as a distributed RLC network. The employed two effective capacitance values capture the nonlinear behavior of the driver. The lossy transmission line approach accounts for the impact of inductance when modeling the driving point interconnect load. The new model shows improvements of 9% in the average delay error and 2.2% in the slew rate error compared to SPICE.

A new inductance extraction technique of spiral inductor from measurement fixture is presented. We propose a scalable expression of parasitic inductance for interconnects, and design consideration of test structure accommodating spiral inductor. The simple expression includes mutual inductance between the interconnects with high accuracy. The formula matches a commercial field solver inductance values within 1.4%. The layout of the test structure to reduce magnetic coupling between the spiral and the interconnects allows us to extract the intrinsic inductance of spiral more accurately. The proposed technique requires neither special fixture used for measurement-based method nor skilled worker for precise extraction with the analytical technique used.

This paper demonstrates an on-chip di/dt detector circuit. The di/dt detector circuit consists of a power supply line, an underlying spiral inductor and an amplifier. The mutual inductor induces a di/dt proportional voltage, and the amplifier amplifies and outputs the value. The measurement results show that the di/dt detector output and the voltage difference between a resistor have good agreement. The di/dt reduction by a decoupling capacitor is also measured using the di/dt detector.

This paper describes the effect of power line inductance and smoothing capacitance on a single-phase AC power supply system. Voltage fluctuations were calculated when the three main types of smoothing circuit (capacitor input, choke input, and power factor correction types) were used and the magnitude of power line inductance and smoothing capacitance were changed. First, we show the difference in voltage fluctuation in the case of constant resistance and negative resistance in a DC-DC converter. Second, we show the waveforms for which the power line inductance affects the voltage fluctuation of the AC power supply system. Finally, we propose the boundary condition for the power line inductance affecting the voltage fluctuation of the AC power supply system and estimate AC power supply system stability.

In recent years the size of transformer in a DC-DC converter becomes smaller and thinner for power module type application. It results in the increase of the leakage inductances because the number of turns of the secondary winding becomes smaller. This paper presents the analysis of static and dynamic characteristics of the novel flyback converter proposed before, and clarifies that the transformer's leakage inductances deteriorate the static load regulation, but improve the dynamic stability by increasing the dumping factor.

Loss compensation in a RF CMOS active inductor with using a capacitor is proposed. This simple compensation technique yields a negative conductance characteristic that can compensate for the constant internal loss of active devices. Simulation results show that the inductor obtains a maximum Q-value of 1.2E8, an inductance value in the range of 50 nH to 450 nH, and a 1.4E-6 Ω of minimum total equivalent loss in the range of 0.6 GHz to 1.3 GHz.

An RF CMOS active inductor with a novel loss compensation circuit network is proposed. Performance of this active inductor can be improved by adding a novel network, which simultaneously reduces parallel and series losses. Consequently, this technique not only increases Q value, inductance, and operating frequency, but also reduces power consumption and circuit complexity. Simulation results show that better performance indices can be achieved, such as minimum total equivalent loss of 1 mΩ, maximum Q value about 3E5, and inductance value from 20 nH to 45 nH in the RF range of 0.6 GHz to 1.6 GHz. Power dissipation is around 1.76 mW under 2.5 V dc supply voltage.

We present a new and efficient approach for extracting on-chip mutual inductances of VLSI interconnects by applying approximation formulae. The equations are based on the assumption of filaments or bars of finite width and zero thickness and are derived through Taylor's expansion of the exact formula for mutual inductance between filaments. Despite the assumption of uniform current density in each of the bars, the model is sufficiently accurate for the interconnections of current and future LSIs because the skin and proximity effects do not affect most wires. Expression of the equations in polynomial form provides a balance between accuracy and computational complexity. These equations are mapped according to the geometric structures for which they are most suitable in minimizing the runtime of inductance calculation while retaining the required accuracy. Within geometrical constraints, the wires are of arbitrary specification. Results of a comprehensive evaluation based on the ITRS-specified global wiring structure for 2003 shows that the inductance values were extracted by using the proposed approach, and they were within several percent of the values obtained by using commercial three-dimensional (3-D) field solvers. The efficiency of the proposed approach is also demonstrated by extraction from a real layout design that has 300-k interconnecting segments.

A formula-based approach for extracting the inductance of on-chip VLSI interconnections is presented. All of the formulae have been previously proposed and are well-known, but the degrees of accuracy they provide in this context have not previously been examined. The accuracy of the equations for a 0.1 µm technology node is evaluated through comparison of their results with those of 3-D field solvers. Comprehensive evaluation has proven that the maximum relative error of self- and mutual inductances as calculated by the formulae are less than 5% for parallel wires and less than 13% for angled wires, when wire width is limited to no more than 10 times the minimum. When applied to a realistic example with 43 wire segments, a program using the formula-based approach extracts values more than 60 times faster than a 3-D field solver.

We derive an efficient and simple analytical expression for estimating maximum simultaneous switching noise (SSN) on ground distribution networks in CMOS systems. In order to estimate maximum SSN voltages, we use α-power law MOS model and Taylor's series approximation. The accuracy of the proposed expression is verified by comparing the results with those of previous researches and HSPICE simulations under the contemporary process parameters and environmental conditions. The proposed method predicts the maximum SSN values more accurately when compared to existing approaches even in most practical cases such that there exist some output drivers not in transition.

We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.

The radiation emission in far zones from printed circuit boards (PCBs) is obtained by treating lines on PCBs as transmission lines and calculating the far-field emission due to current distribution on lines. In this paper, we present a more precise circuit model, based on TEM assumption, to decompose the total current into differential-mode current and common-mode current. This circuit model is based on transmission line model, but it considers the effect of ground trace. The finite size ground trace can be viewed as an inductive reactance. A knowledge of the net inductance of the ground trace can aid in the analysis and investigation of PCBs emission. We show the derived equations of the modified transmission lines for the geometrics of practical interest. As time-varying current passes through such ground trace, a voltage drop due to the inductance of the trace will act as a source of the common-mode current. Furthermore, charge stored in capacitance between signal and ground traces will cause the current pulses returning to their source. The magnitudes of currents are slightly unequal in the signal and ground traces, which can cause common-mode current to flow. An unbalanced circuit on a PCB constructed with signal and ground trace pairs will radiate as an asymmetric folded-dipole. By antenna theory, the contribution of differential-mode and common-mode currents to radiated emission of PCBs can be calculated. In addition, comparisons between experimental results and calculation results are also given.

We report on the fabrication and operation of all-NbN single flux quantum (SFQ) circuits with resistively shunted NbN/AlN/NbN tunnel junctions fabricated on silicon substrates. The critical current varied by about 5% in 400 NbN/AlN/NbN junction arrays, where the junction area was 88 µm2. Critical current densities of the NbN/AlN/NbN tunnel junctions showed exponential dependence on the deposition time of the AlN barrier. By using the 12-nm-thick Cu film as shunted resistors, non-hysteretic current-voltage characteristics were achieved. From dc-SQUID measurements, the sheet inductance of our NbN stripline was estimated to be around 1.2 pH at 4.2 K. We designed and fabricated circuits consisting of dc/SFQ converters, Josephson transmission lines, and T flip-flop-based SFQ/dc converters. The circuits demonstrated correct operation with a bias margin of more than 15% at 4.2 K.

This paper presents a novel distortion compensation technique using an active inductor. First, we describe the input-reflection-coefficient characteristics of a GaAs MESFET active inductor when input power increases. We show that the inductor exhibits positive amplitude deviation and negative/positive phase deviation as the input power increases when the biases of the FETs are set appropriately. The chip size of the fabricated active inductor is less than 0.52 mm2. Then, we show that third-order intermodulation is improved when the active inductor is used as a predistortion linearizer. Third-order intermodulation was improved over the output range from 14 dBm to 25 dBm, and at the output of 15 dBm, third-order intermodulation was improved approximately by 9 dB when the predistortion linearizer was introduced. The active inductor can thus function as a miniaturized predistortion linearizer by using it in the input matching circuit of a power amplifier. This technique can be applied in the miniaturization of wireless communication devices.

Resonant properties of resistively shunted tunnel junctions dominate the high-frequency performance of Josephson array oscillators. To improve the operating frequency, we have developed resistively shunted Nb/AlOx/Nb tunnel junctions with a small parasitic inductance. The inductance was minimized by reducing the inductive length between the tunnel junction and the contact hole to be about 1µm. By fitting the measured I-V characteristics of the shunted tunnel junction to the simulated characteristics, we estimated the inductance to be about 105 fH. The analysis of resonant properties showed that the shunted tunnel junctions with the small parasitic inductance have a high-frequency performance up to the Nb gap frequency. Josephson array oscillators using 11 such junctions were designed and fabricated to operate at 650 GHz and 1 THz. Shapiro steps induced by Josephson oscillation were clearly observed up to 1 THz. By fitting the step heights to the simulated results, we estimated the output power of the Josephson oscillator delivered to the load resistor to be about 10 µW at 625 GHz and 50 nW at 1 THz.

Recently fiber optic links have been applied to radio signal distribution networks and also to signal feeder networks for phased array antennas, because they are able to offer wide bandwidth for achieving the high bit-rates and large capacity needed in the multimedia age. In these networks, a great many modules are needed to convert optical signals to radio signals. In order to reduce the complexity and cost of these modules, direct optical control techniques, which inject optical signals directly into microwave circuits, are very attractive. Thus, this paper proposes a novel optical control technique using tunable inductance circuits. This technique employs direct illumination as a means of optically tuning the inductance. Since the inductance value is inversely proportional to the square of the transconductance, it varies widely when the FET is directly illuminated. With direct illumination, the measured inductance variation in an experimental inductance circuit built with Pseudomorphic AlGaAs/InGaAs/GaAs HEMTs is more than 20 % from 0.5 to 2 GHz. As an application, a direct optically controlled oscillator was fabricated. The measured optical tuning range of the oscillation frequency is more than 19 % with an output power of -51 dBm. This is a promising technique for a variety of devices, including optically controlled oscillators, filters, phase shifters, and active antennas.

For high frequency video signals, display monitors for personal computers are required to shift from the horizontal scanning frequency fH=15.75 kHz for conventional TV broadcasting to fH=64 to 80 kHz, which is called XGA. Shifting to high frequencies and restrictions on the withstand voltage of horizontal transistors decrease the inductance of deflection yokes, which is an obstacle in manufacturing deflection yokes. A study was undertaken on an operation to permit deflection/high voltage integrated operation while keeping the inductance of the deflection yoke high. This paper reports the results.

This paper is described on the realization of simulated inductance cercuit with parallel negative conductance and its application for an oscillator. The design's condition for realizing the circuit needs stability, narrow expance of elements, larger dynamic-range and lower sensitivity. A new floating simulated inductance circuit with parallel nagative conductance with two operational amplifiers, four resistors, and four capacitors is created by using the design's algorithm. And the elements sensitivity of the simulated circuit is superior to that of the conventional circuits. By experimenting with a resonance circuit, the author tested the sinusoidal oscillator's circuit of a parallel -GLC as an application in order to confirm the operation of the simulated inductance circuit with parallel negative conductance.