It is important to consider curvature properties around the control points to produce natural-looking results in the vector illustration. C2 interpolating splines satisfy point interpolation with local support. Unfortunately, they cannot control the sharpness of the segment because it utilizes trigonometric function as blending function that has no degree of freedom. In this paper, we alternate the definition of C2 interpolating splines in both interpolation curve and blending function. For the interpolation curve, we adopt a rational Bézier curve that enables the user to tune the shape of curve around the control point. For the blending function, we generalize the weighting scheme of C2 interpolating splines and replace the trigonometric weight to our novel hyperbolic blending function. By extending this basic definition, we can also handle exact non-C2 features, such as cusps and fillets, without losing generality. In our experiment, we provide both quantitative and qualitative comparisons to existing parametric curve models and discuss the difference among them.

An audio signal level compressor is presented, which is based on the approximation algorithm using an interpolating polynomial. To implement a compression characteristic in a digital audio system, a power calculation with fractional numbers is required and it is difficult to be performed directly in digital circuits. We introduce a polynomial expression to approximate the power operation, then the gain calculation is easily performed with a number of additions, multiplications and a division. Newton's interpolation formula is used to calculate the compression characteristics in a very short time and the obtained compression characteristics are very close to the ideal ones.

An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.

A current-mode folding and interpolating analog to digital converter (ADC) architecture with multiplied folding amplifiers is proposed in this paper. A current-mode multiplied folding amplifier is employed not only to reduce the number of reference current source, but also to decrease a power dissipation within the ADC. The proposed ADC for 12 bit was designed by a 0.65 µm n-well CMOS single poly/double metal process. The simulated result shows a differential nonlinearity (DNL) of 0.5LSB, an integral nonlinearity (INL) of 1.0LSB, 20 Ms/s of the data conversion rate, and the power dissipation of 180 mW with a power supply of 5 V.