An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter

Seung-Chan HEO; Young-Chan JANG; Sang-Hune PARK; Hong-June PARK

An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter

Seung-Chan HEO, Young-Chan JANG, Sang-Hune PARK, Hong-June PARK

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An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.

Publication: IEICE TRANSACTIONS on Electronics Vol.E86-C No.4 pp.676-681

Publication Date: 2003/04/01

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Type of Manuscript: LETTER

Category: Electronic Circuits

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Seung-Chan HEO, Young-Chan JANG, Sang-Hune PARK, Hong-June PARK, "An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter" in IEICE TRANSACTIONS on Electronics, vol. E86-C, no. 4, pp. 676-681, April 2003, doi: .
Abstract: An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e86-c_4_676/_p

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@ARTICLE{e86-c_4_676,
author={Seung-Chan HEO, Young-Chan JANG, Sang-Hune PARK, Hong-June PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter},
year={2003},
volume={E86-C},
number={4},
pages={676-681},
abstract={An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.},
keywords={},
doi={},
ISSN={},
month={April},}

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TY - JOUR
TI - An 8-Bit 200 MS/s CMOS Folding/Interpolating Analog-to-Digital Converter
T2 - IEICE TRANSACTIONS on Electronics
SP - 676
EP - 681
AU - Seung-Chan HEO
AU - Young-Chan JANG
AU - Sang-Hune PARK
AU - Hong-June PARK
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2003
AB - An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.
ER -