This paper proposes an efficient scheduling algorithm for the layered decoding of block low-density parity-check (LDPC) codes. To efficiently configure check node-based scheduling groups, the proposed algorithm utilizes the base matrix of the block LDPC code for a block-by-block scheduling group configuration; i.e., the proposed algorithm generates a scheduling group of check nodes, satisfying the weight condition of the layered decoding, which is performed in block units (including several check nodes). Therefore, unlike the conventional scheduling algorithms performed in node units, the proposed algorithm can efficiently generate scheduling groups for layered decoding at low computational complexity and memory requirements. In addition, to accelerate the decoding convergence speed, check nodes are allocated in each scheduling group such that messages from check nodes up to the current group are delivered as evenly as possible to bit nodes. Simulation results confirm that the proposed algorithm can accelerate decoding convergence compared to other block-based scheduling algorithms for layered decoding of block LDPC codes.

This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.

In this letter, we analyze the convergence speed of layered decoding of block-type low-density parity-check codes and verify that the layered decoding gives faster convergence speed than the sequential decoding with randomly selected check node subsets. Also, it is shown that using more subsets than the maximum variable node degree does not improve the convergence speed.