This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.
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Meng XU, Xincun JI, Jianhui WU, Meng ZHANG, "A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks" in IEICE TRANSACTIONS on Communications,
vol. E96-B, no. 4, pp. 939-947, April 2013, doi: 10.1587/transcom.E96.B.939.
Abstract: This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/transcom.E96.B.939/_p
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@ARTICLE{e96-b_4_939,
author={Meng XU, Xincun JI, Jianhui WU, Meng ZHANG, },
journal={IEICE TRANSACTIONS on Communications},
title={A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks},
year={2013},
volume={E96-B},
number={4},
pages={939-947},
abstract={This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.},
keywords={},
doi={10.1587/transcom.E96.B.939},
ISSN={1745-1345},
month={April},}
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TY - JOUR
TI - A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks
T2 - IEICE TRANSACTIONS on Communications
SP - 939
EP - 947
AU - Meng XU
AU - Xincun JI
AU - Jianhui WU
AU - Meng ZHANG
PY - 2013
DO - 10.1587/transcom.E96.B.939
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E96-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2013
AB - This paper presents a low-power LDPC decoder that can be used in Multimedia Wireless Sensor Networks. Three low power design techniques are proposed in the decoder design: a layered decoding algorithm, a modified Benes network and a modified memory bypassing scheme. The proposed decoder is implemented in TSMC 0.13 µm, 1.2 V CMOS process. Experiments show that when the clock frequency is 32 MHz, the power consumption of the proposed decoder is 38.4 mW, the energy efficiency is 53.3 pJ/bit/ite and the core area is 1.8 mm2.
ER -