The response of differential pairs against low-frequency substrate voltage variation is captured in a combined transistor and substrate network models. The model generation is regularized for variation of transistor geometries including channel sizes, fingering and folding, and the placements of guard bands. The expansion of the models for full-chip substrate noise analysis is also discussed. The substrate sensitivity of differential pairs is evaluated through on-chip substrate coupling measurements in a 90 nm CMOS technology with more than 64 different geometries and operating conditions. The trends and strengths of substrate sensitivity are shown to be well consistent between simulation and measurements.

Substrate coupling of radio frequency (RF) components is represented by equivalent circuits unifying a resistive mesh network with lumped capacitors in connection with the backside of device models. Two-port S-parameter test structures are used to characterize the strength of substrate coupling of resistors, capacitors, inductors, and MOSFETs in a 65 nm CMOS technology with different geometries and dimensions. The consistency is finely demonstrated between simulation with the equivalent circuits and measurements of the test structures, with the deviation of typically less than 3 dB for passive and 6 dB for active components, in the transmission properties for the frequency range of interest up to 8 GHz.