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Takeshi YOSHIDA Yoshihiro MASUI Ryoji EKI Atsushi IWATA Masayuki YOSHIDA Kazumasa UEMATSU
To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100 µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39 dB at the bandwidth of the neural signal and the gain reduction of 20 dB at AC supply noise of 60 Hz were obtained. The input equivalent noise and power dissipation were 90 nV/root-Hz and 90 µW at a supply voltage of 1.5 V, respectively.
Takeshi YOSHIDA Takayuki MASHIMO Miho AKAGI Atsushi IWATA Masayuki YOSHIDA Kazumasa UEMATSU
A neural-signal sensing system with multi-input-channels was designed utilizing a new chopper amplifier with direct connected to a multiplexer. The proposed system consists of multiplexers, chopper amplifiers, a multi-mode analog-to-digital converter (ADC), and a wireless transmitter. It enables to measure 50-channel signals at the same time, which are selected out of 100 channels to detect useful information. The test chip including 10-channel-inputs chopper-amplifier and multi-mode ADC, that was designed and fabricated with a mixed signal 0.35-µm CMOS technology. Utilizing the proposed direct chopper input scheme and the shared chopper amplifier, the circuits was designed with a small area of 9.4 mm2. High accuracy channel selecting and multiplexing operations were confirmed, and an equivalent input noise of 10-nV/root-Hz was obtained with test chip measurements. Power dissipation of the chopper amplifier and the ADC were 6.0-mW and 2.5-mW at a 3-V supply voltage, respectively.