This paper proposes a multibeam digital predistorter (DPD) that suppresses intercarrier interference caused by nonlinear distortions of power amplifiers (PAs) while reducing the power consumption of a multibeam array antenna transmitter. The proposed DPD reduces power consumption by allowing the final PAs of the array antenna transmitter to operate in a highly efficient nonlinear mode and compensating for the nonlinear distortions of the PAs with a unified dedicated DPD per subarray. Additionally, it provides the required high-quality signal transmission for high throughputs, such as realizing a 256-quadrature amplitude modulation (QAM) transmission instead of a 64-QAM transmission. Specifically, it adds an inverse-component signal to cancel the interference from an adjacent carrier of another beam. Consequently, it can suppress the intercarrier interference in the beam direction and improve the error vector magnitude (EVM) during the multibeam transmission, in which the frequency bands of the beams are adjacent. The experimental results obtained for two beams at 28.0 and 28.4GHz demonstrate that, compared with the previous single-beam DPD, the proposed multibeam DPD can improve the EVM. Also, they demonstrate that the proposed DPD can achieve an EVM value of <3%, which completely satisfies the 3GPP requirements for a 256-QAM transmission.

Fully integrated CMOS power amplifiers (PAs) with a two-winding and single-winding combined transformer (TS transformer) are presented. The general analysis of the TS transformer and other power-combining transformers, i.e., the series-combining transformer and parallel-combining transformer, is presented in terms of the transformer design parameters. Compared with other power-combining transformers, the proposed power-combining TS transformer offers high-efficiency with a compact form factor. In addition, a fully integrated CMOS PA using the TS transformer with multi-gated transistors (MGTRs) and adaptive bias circuit has been proposed to improve linearity. The proposed PAs are implemented using 65-nm CMOS technology. The implemented PA with the TS transformer achieves a saturated output power of 26.7 dBm with drain efficiency (DE) of 47.7%. The PA achieves 20.13-dBm output power with 21.4% DE while satisfying the -25-dB error vector magnitude (EVM) requirement when tested with the WLAN 802.11g signal. The implemented PA using the TS transformer with MGTRs and adaptive bias circuit achieves the -30-dB EVM requirement up to an output power of 17.13 dBm with 10.43% DE when tested using the WLAN 802.11ac signal.

This paper proposes a method for reducing the peak-to-average power ratio (PAPR) at the output signal of a digital predistortion linearizer (DPDL) that compensates for frequency dependent intermodulation distortion (IMD) components. The proposed method controls the amplitude and phase values of the frequency components corresponding to the transmission bandwidth of the output signal. A DPDL employing the proposed method simultaneously provides IMD component cancellation of out-of-band components and PAPR reduction at the output signal. This paper identifies the amplitude and phase conditions to minimize the PAPR. Experimental results based on a 2-GHz band 1-W class power amplifier show that the proposed method improves the drain efficiency of the power amplifier when degradation is allowed in the error vector magnitude. To the best knowledge of the authors, this is the first PAPR reduction method for DPDL that reduces the PAPR while simultaneously compensating for IMD components.

This paper presents a wideband digital predistortion (DPD) architecture suitable for wideband wireless systems, such as IEEE 802.11ad/WiGig, where low oversampling ratio of the digital-to-analog converter (DAC) is a bottleneck for available linearization bandwidth. In order to overcome the bandwidth limitation in the conventional DPD, the proposed DPD introduces a complex coefficient filter in the DPD signal processing, which enables it to achieve asymmetric linearization. This approach effectively suppresses one side of adjacent channel leakages with twice the bandwidth as compared to the conventional DPD. The concept is verified through system simulation and measurements. Using a scaled model of a 2 GHz RF carrier frequency, the measurement shows a 4.2 dB advantage over the conventional DPD in terms of adjacent channel leakage.

This paper describes the design method of a broadband CMOS stacked power amplifier using harmonic control over wide bandwidths in a 0.11,$mu $m standard CMOS process. The high-efficiency can be obtained over wide bandwidths by designing a load impedance circuit as purely reactive as possible to the harmonics with broadband fundamental matching, which is based on continuous Class-F mode of operation. Furthermore, the stacked topology overcomes the low breakdown voltage limit of CMOS transistor and increases output impedance. With a 5-V supply and a fixed matching circuitry, the suggested power amplifier (PA) achieves a saturated output power of over 26.7,dBm and a drain efficiency of over 38% from 1.6,GHz to 2.2,GHz. In W-CDMA modulation signal measurements, the PA generates linear power and power added efficiency of over 23.5,dBm and 33% (@ACLR $=-33$,dBc).

In this paper, a robust fractional order memory polynomial pre-distorter with two novel schemes to conduct digital base-band power amplifier pre-distortion is proposed. For the first scheme, fractional order terms are included in the conventional memory polynomial containing the odd and even order polynomial terms, which is called Scheme One. The second scheme, called Scheme Two, simply replaces even order polynomial terms with fractional order polynomial terms to improve the linear performance of power amplifiers. The mathematical expressions for these two schemes are derived. The computer simulations and numerical analysis show that, compared with the conventional pre-distortion methods, 11 dB and 8.5 dB more out-of-band suppression gain can be obtained by Scheme One and Scheme Two, respectively. Corresponding FPGA realization shows that the two schemes are cost-effective in terms of hardware resources.

With the smaller layout area and parasitic capacitance under the same electrostatic discharge (ESD) robustness, silicon-controlled rectifier (SCR) has been used as an effective on-chip ESD protection device in radio-frequency (RF) IC. In this paper, SCR's with the waffle layout structures are studied to minimize the parasitic capacitance and the variation of the parasitic capacitance within ultra-wide band (UWB) frequencies. With the reduced parasitic capacitance and capacitance variation, the degradation on UWB RF circuit performance can be minimized. Besides, the fast turn-on design on the low-capacitance SCR without increasing the I/O loading capacitance is investigated and applied to an UWB RF power amplifier (PA). The PA co-designed with SCR in the waffle layout structure has been fabricated. Before ESD stress, the RF performances of the ESD-protected PA are as well as that of the unprotected PA. After ESD stress, the unprotected PA is seriously degraded, whereas the ESD-protected PA still keeps the performances well.

This paper investigates limitations of adjacent channel power ratio (ACPR) improvement in predistortion (pre-D) linearizer used with nonlinear RF power amplifiers (PAs) when the PA model is not perfectly acquired in pre-D design. The error between the physical PA and the nonlinear model is expanded by pre-D function and its power spectral density (PSD) works as limitations in ACPR improvement of the pre-D linearizer. An analytical estimation of ACPR limitations in RF PAs driven by digitally modulated input signal is derived using a formulation of autocorrelation function. The analysis technique is validated with the example of the memory polynomial PA model with the quasi-memoryless pre-D linearizer. The technique is also verified by comparing predicted ACPR limitation with measured limitation for a RF PA with 802.11g input signal.

A 2.4/5.2 GHz CMOS dual band driver stages with integrated 5.2 GHz power amplifier is presented in this work. For more accurate simulation of high power CMOS amplifier, a re-optimized macro NMOS model is used, whose nonlinear model accuracy is enhanced and its validity is proved by comparing load pull simulation with measurement. In order to achieve band selection, it has switched matching circuits at the first stage and SPDT path switch following them. At 2.4 GHz and 5.2 GHz bands, the achieved values of Psat of the switched amplifier are 9.7 dBm and 19.5 dBm, respectively. The achieved PAE is 15.3% at 5.2 GHz.