This paper presents a novel electrical polarization forming antenna for mobile satellite communication systems using linear polarization. To electrically form the desired polarization, it is necessary to excite the two orthogonal polarization antenna planes with appropriate weights. The proposed antenna uses digitally-based polarization and calibration functions to characterize the two RF paths. The calibration techniques used are critical to accurately forming the desired polarization. Proposed calibration techniques are very simple; the feedback signal consists of just amplitude levels. The proposals are validated by polarization forming measurements conducted on a fabricated antenna.

This paper proposes a novel Doppler frequency shift compensation technique to achieve terrestrial and low earth orbit (LEO) satellite dual mode DS/CDMA terminals robust to high Doppler shift and multipath fading. In order to satisfy the requirements of wide dynamic range and high accuracy simultaneously, the proposed scheme employs two stage compensation scheme, i.e., coarse compensation to keep dynamic range of about 100 kHz and fine compensation to satisfy its resolution of about 30 Hz, using block demodulation technique. Computer simulation results show that the proposed scheme can sufficiently compensate for the offset frequency up to the range of about 100 kHz at the terrestrial and LEO satellite combined mobile communication systems.

An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.