Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--

Katsuhiko KAWAZOE; Shunji HONDA; Shuji KUBOTA; Shuzo KATO

Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--

Katsuhiko KAWAZOE, Shunji HONDA, Shuji KUBOTA, Shuzo KATO

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An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.12 pp.1888-1894

Publication Date: 1994/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)

Category: Multimedia System LSIs

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Katsuhiko KAWAZOE, Shunji HONDA, Shuji KUBOTA, Shuzo KATO, "Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 12, pp. 1888-1894, December 1994, doi: .
Abstract: An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.
URL: https://globals.ieice.org/en_transactions/electronics/10.1587/e77-c_12_1888/_p

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@ARTICLE{e77-c_12_1888,
author={Katsuhiko KAWAZOE, Shunji HONDA, Shuji KUBOTA, Shuzo KATO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--},
year={1994},
volume={E77-C},
number={12},
pages={1888-1894},
abstract={An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Ultra-High-Speed and Universal-Coding-Rate Viterbi Decoder VLSIC--SNUFEC VLSI--
T2 - IEICE TRANSACTIONS on Electronics
SP - 1888
EP - 1894
AU - Katsuhiko KAWAZOE
AU - Shunji HONDA
AU - Shuji KUBOTA
AU - Shuzo KATO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1994
AB - An Ultra-high-speed (higher than 60 MHz) Viterbi decoder VLSIC with coding rates from one-half to fifteen-sixteenth and a constraint length of seven for forward error correction (FEC) has been developed using 0.8-µm semicustom CMOS LSIC technology and a newly developed high-speed ACS circuit. To reduce power consumption of the one-chip Viterbi decoder, a universal-coding-rate scarce-state-transition (SST) Viterbi decoding scheme and low-power-consumption burst-mode-selection (BMS) path memory have been proposed and employed to the developed VLSIC. In addition, a new maximum-likelihood-decision (MLD) circuit for the SST Viterbi decoder has been developed. The total power consumption of the developed chip is reduced to 75% of the conventional one and the developed Viterbi decodar VLSIC achieves a maximum operation speed of 60 MHz. It achieves near theoretical net coding-gain performance for various coding rates.
ER -