To improve measurement accuracy and speed, a switched-capacitor capacitance measurement circuit with the vernier scale is developed. Its process consists of a coarse measurement by charge-balancing A-D conversion and a fine measurement by single-slope A-D conversion. a prototype using discrete components confirms the principles of operation.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

In this paper, a design method is described for very low sensitivity fully-balanced narrow-band band-pass switched-capacitor filters (SCF's) whose worst-case sensitivities of the amplitude responses become zero at every reflection zero. The proposed method is based on applying the low-pass to high-pass transformation, the pseudo two-path technique and the capacitance-ratio reduction technique to very low sensitivity low-pass SC ladder filters. A design example of the band-pass SCF with a quality factor Q250 is given to verify the proposed method. The remarkable advantages of this approach are very low sensitivity to element-value variations, a small capacitance spread, a small total capacitance, and clock-feedthrough noise immunity inside the passband.