Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems

Kwangsup SO; Jinsang KIM; Won-Kyung CHO; Young-Soo KIM; Doug Young SUH

doi:10.1093/ietcom/e89-b.12.3242

Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems

Kwangsup SO, Jinsang KIM, Won-Kyung CHO, Young-Soo KIM, Doug Young SUH

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Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 44 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 44, 48, 412, ... 1616. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 µm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.

Publication: IEICE TRANSACTIONS on Communications Vol.E89-B No.12 pp.3242-3249

Publication Date: 2006/12/01

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Online ISSN: 1745-1345

DOI: 10.1093/ietcom/e89-b.12.3242

Type of Manuscript: Special Section PAPER (Special Section on Software Defined Radio Technology and Its Applications)

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Kwangsup SO, Jinsang KIM, Won-Kyung CHO, Young-Soo KIM, Doug Young SUH, "Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems" in IEICE TRANSACTIONS on Communications, vol. E89-B, no. 12, pp. 3242-3249, December 2006, doi: 10.1093/ietcom/e89-b.12.3242.
Abstract: Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 44 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 44, 48, 412, ... 1616. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 µm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.
URL: https://globals.ieice.org/en_transactions/communications/10.1093/ietcom/e89-b.12.3242/_p

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@ARTICLE{e89-b_12_3242,
author={Kwangsup SO, Jinsang KIM, Won-Kyung CHO, Young-Soo KIM, Doug Young SUH, },
journal={IEICE TRANSACTIONS on Communications},
title={Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems},
year={2006},
volume={E89-B},
number={12},
pages={3242-3249},
abstract={Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 44 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 44, 48, 412, ... 1616. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 µm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.},
keywords={},
doi={10.1093/ietcom/e89-b.12.3242},
ISSN={1745-1345},
month={December},}

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TY - JOUR
TI - Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems
T2 - IEICE TRANSACTIONS on Communications
SP - 3242
EP - 3249
AU - Kwangsup SO
AU - Jinsang KIM
AU - Won-Kyung CHO
AU - Young-Soo KIM
AU - Doug Young SUH
PY - 2006
DO - 10.1093/ietcom/e89-b.12.3242
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E89-B
IS - 12
JA - IEICE TRANSACTIONS on Communications
Y1 - December 2006
AB - Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 44 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 44, 48, 412, ... 1616. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 µm libraries are used, the chip area and critical path of the proposed architecture are 186,411 gates and 2.79 ns, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.
ER -