A Digitalized Quadrature Modulator for Fast Frequency Hopping

Kazuhiko SEKI; Tetsu SAKATA; Shuzo KATO

A Digitalized Quadrature Modulator for Fast Frequency Hopping

Kazuhiko SEKI, Tetsu SAKATA, Shuzo KATO

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This paper proposes a digitalized quadrature modulator for burst-by-burst carrier frequency hopping in TDMA-TDD systems. It employs digital frequency synthesis and a multiplexing modulation scheme to give the frequency offset to the modulated IF signal. Moreover, to reduce the frequency settling time of the RF synthesizer below the guard time duration, a phase and frequency preset (PFP) PLL synthesizer is employed. By employing the digital modulation scheme, the proposed modulator needs only one D/A converter, as a result, the complexity of adjusting the DC offset and amplitude between analog signals of the in-phase and the quadrature phase is eliminated. The performance of the proposed modulator is analyzed theoretically and simulated by computers. Theoretical analyses show that the frequency settling time with 15MHz hopping width in the 1900MHz band is reduced by more than 75% from that of the conventional synthesizer. The settling time is less than 40µs which is shorter than the typical guard time of the burst signal format. The analyses also show that the power consumption of the proposed modulator is lower than that of the conventional modulator employing a full band digital frequency converter. Furthermore, the computer simulation confirms that the power spectra and the constellations of the proposed modulator for the coherent and the π/4-shift QPSK modulation schemes can be successfully generated.

Publication: IEICE TRANSACTIONS on Communications Vol.E77-B No.5 pp.656-662

Publication Date: 1994/05/25

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Type of Manuscript: PAPER

Category: Radio Communication

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Kazuhiko SEKI, Tetsu SAKATA, Shuzo KATO, "A Digitalized Quadrature Modulator for Fast Frequency Hopping" in IEICE TRANSACTIONS on Communications, vol. E77-B, no. 5, pp. 656-662, May 1994, doi: .
Abstract: This paper proposes a digitalized quadrature modulator for burst-by-burst carrier frequency hopping in TDMA-TDD systems. It employs digital frequency synthesis and a multiplexing modulation scheme to give the frequency offset to the modulated IF signal. Moreover, to reduce the frequency settling time of the RF synthesizer below the guard time duration, a phase and frequency preset (PFP) PLL synthesizer is employed. By employing the digital modulation scheme, the proposed modulator needs only one D/A converter, as a result, the complexity of adjusting the DC offset and amplitude between analog signals of the in-phase and the quadrature phase is eliminated. The performance of the proposed modulator is analyzed theoretically and simulated by computers. Theoretical analyses show that the frequency settling time with 15MHz hopping width in the 1900MHz band is reduced by more than 75% from that of the conventional synthesizer. The settling time is less than 40µs which is shorter than the typical guard time of the burst signal format. The analyses also show that the power consumption of the proposed modulator is lower than that of the conventional modulator employing a full band digital frequency converter. Furthermore, the computer simulation confirms that the power spectra and the constellations of the proposed modulator for the coherent and the π/4-shift QPSK modulation schemes can be successfully generated.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/e77-b_5_656/_p

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@ARTICLE{e77-b_5_656,
author={Kazuhiko SEKI, Tetsu SAKATA, Shuzo KATO, },
journal={IEICE TRANSACTIONS on Communications},
title={A Digitalized Quadrature Modulator for Fast Frequency Hopping},
year={1994},
volume={E77-B},
number={5},
pages={656-662},
abstract={This paper proposes a digitalized quadrature modulator for burst-by-burst carrier frequency hopping in TDMA-TDD systems. It employs digital frequency synthesis and a multiplexing modulation scheme to give the frequency offset to the modulated IF signal. Moreover, to reduce the frequency settling time of the RF synthesizer below the guard time duration, a phase and frequency preset (PFP) PLL synthesizer is employed. By employing the digital modulation scheme, the proposed modulator needs only one D/A converter, as a result, the complexity of adjusting the DC offset and amplitude between analog signals of the in-phase and the quadrature phase is eliminated. The performance of the proposed modulator is analyzed theoretically and simulated by computers. Theoretical analyses show that the frequency settling time with 15MHz hopping width in the 1900MHz band is reduced by more than 75% from that of the conventional synthesizer. The settling time is less than 40µs which is shorter than the typical guard time of the burst signal format. The analyses also show that the power consumption of the proposed modulator is lower than that of the conventional modulator employing a full band digital frequency converter. Furthermore, the computer simulation confirms that the power spectra and the constellations of the proposed modulator for the coherent and the π/4-shift QPSK modulation schemes can be successfully generated.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A Digitalized Quadrature Modulator for Fast Frequency Hopping
T2 - IEICE TRANSACTIONS on Communications
SP - 656
EP - 662
AU - Kazuhiko SEKI
AU - Tetsu SAKATA
AU - Shuzo KATO
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E77-B
IS - 5
JA - IEICE TRANSACTIONS on Communications
Y1 - May 1994
AB - This paper proposes a digitalized quadrature modulator for burst-by-burst carrier frequency hopping in TDMA-TDD systems. It employs digital frequency synthesis and a multiplexing modulation scheme to give the frequency offset to the modulated IF signal. Moreover, to reduce the frequency settling time of the RF synthesizer below the guard time duration, a phase and frequency preset (PFP) PLL synthesizer is employed. By employing the digital modulation scheme, the proposed modulator needs only one D/A converter, as a result, the complexity of adjusting the DC offset and amplitude between analog signals of the in-phase and the quadrature phase is eliminated. The performance of the proposed modulator is analyzed theoretically and simulated by computers. Theoretical analyses show that the frequency settling time with 15MHz hopping width in the 1900MHz band is reduced by more than 75% from that of the conventional synthesizer. The settling time is less than 40µs which is shorter than the typical guard time of the burst signal format. The analyses also show that the power consumption of the proposed modulator is lower than that of the conventional modulator employing a full band digital frequency converter. Furthermore, the computer simulation confirms that the power spectra and the constellations of the proposed modulator for the coherent and the π/4-shift QPSK modulation schemes can be successfully generated.
ER -