Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions

Hideaki YAMANAKA; Hirotaka SAITO; Hirotoshi YAMADA; Harufusa KONDOH; Hiromi NOTANI; Yoshio MATSUDA; Kazuyoshi OSHIMA

Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions

Hideaki YAMANAKA, Hirotaka SAITO, Hirotoshi YAMADA, Harufusa KONDOH, Hiromi NOTANI, Yoshio MATSUDA, Kazuyoshi OSHIMA

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A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.

Publication: IEICE TRANSACTIONS on Communications Vol.E79-B No.8 pp.1109-1120

Publication Date: 1996/08/25

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Type of Manuscript: PAPER

Category: Switching and Communication Processing

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Hideaki YAMANAKA, Hirotaka SAITO, Hirotoshi YAMADA, Harufusa KONDOH, Hiromi NOTANI, Yoshio MATSUDA, Kazuyoshi OSHIMA, "Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions" in IEICE TRANSACTIONS on Communications, vol. E79-B, no. 8, pp. 1109-1120, August 1996, doi: .
Abstract: A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/e79-b_8_1109/_p

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@ARTICLE{e79-b_8_1109,
author={Hideaki YAMANAKA, Hirotaka SAITO, Hirotoshi YAMADA, Harufusa KONDOH, Hiromi NOTANI, Yoshio MATSUDA, Kazuyoshi OSHIMA, },
journal={IEICE TRANSACTIONS on Communications},
title={Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions},
year={1996},
volume={E79-B},
number={8},
pages={1109-1120},
abstract={A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.},
keywords={},
doi={},
ISSN={},
month={August},}

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TY - JOUR
TI - Shared Multibuffer ATM Switches with Hierarchical Queueing and Multicast Functions
T2 - IEICE TRANSACTIONS on Communications
SP - 1109
EP - 1120
AU - Hideaki YAMANAKA
AU - Hirotaka SAITO
AU - Hirotoshi YAMADA
AU - Harufusa KONDOH
AU - Hiromi NOTANI
AU - Yoshio MATSUDA
AU - Kazuyoshi OSHIMA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E79-B
IS - 8
JA - IEICE TRANSACTIONS on Communications
Y1 - August 1996
AB - A new ATM switch architecture, named shared multibuffering, features great advantages on memory access speed for a large switch, and overall size of buffer memories to achieve excellent cell-loss performance. We have developed a 622-Mb/s 88 shared multibuffer ATM switch with multicast functions and hierarchical queueing functions to accommodate 156-Mb/s, 622-Mb/s and 2.4-Gb/s interfaces. Implementation of the shared multibuffer ATM switch is described with respect to the four sorts of 0.8-µm BiCMOS LSIs and ATM switch boards. The switch board/type-1, with C1-LSI, allows to accommodate effectively 156-Mb/s and 622-Mb/s interfaces, which is suitable for an ATM access system. The switch board/type-2, with C2-LSI, can provide multicast functions and accommodate a 2.4-Gb/s interface. By using four switch boards, it is possible to apply them to a 2.4-Gb/s ATM loop system.
ER -