Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes

Jianjun MU; Xiaopeng JIAO; Jianguang LIU; Rong SUN

doi:10.1587/transcom.E94.B.1725

Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes

Jianjun MU, Xiaopeng JIAO, Jianguang LIU, Rong SUN

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Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.

Publication: IEICE TRANSACTIONS on Communications Vol.E94-B No.6 pp.1725-1727

Publication Date: 2011/06/01

Publicized

Online ISSN: 1745-1345

DOI: 10.1587/transcom.E94.B.1725

Type of Manuscript: LETTER

Category: Fundamental Theories for Communications

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Jianjun MU, Xiaopeng JIAO, Jianguang LIU, Rong SUN, "Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes" in IEICE TRANSACTIONS on Communications, vol. E94-B, no. 6, pp. 1725-1727, June 2011, doi: 10.1587/transcom.E94.B.1725.
Abstract: Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.
URL: https://globals.ieice.org/en_transactions/communications/10.1587/transcom.E94.B.1725/_p

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@ARTICLE{e94-b_6_1725,
author={Jianjun MU, Xiaopeng JIAO, Jianguang LIU, Rong SUN, },
journal={IEICE TRANSACTIONS on Communications},
title={Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes},
year={2011},
volume={E94-B},
number={6},
pages={1725-1727},
abstract={Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.},
keywords={},
doi={10.1587/transcom.E94.B.1725},
ISSN={1745-1345},
month={June},}

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TY - JOUR
TI - Parity-Check Matrix Extension to Lower the Error Floors of Irregular LDPC Codes
T2 - IEICE TRANSACTIONS on Communications
SP - 1725
EP - 1727
AU - Jianjun MU
AU - Xiaopeng JIAO
AU - Jianguang LIU
AU - Rong SUN
PY - 2011
DO - 10.1587/transcom.E94.B.1725
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E94-B
IS - 6
JA - IEICE TRANSACTIONS on Communications
Y1 - June 2011
AB - Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.
ER -