Quasi cyclic LDPC (QC-LDPC) codes consisting of circulant permutation matrices (CPM-QC-LDPC) are one of the most attractive types of LDPC codes due to their many advantages. In this paper, we mainly do some research on CPM-QC-LDPC codes. We first propose a two-stage decoding scheme mainly based on parity check matrix transform (MT), which can efficiently improve the bit error rate performance. To optimize the tradeoff between hardware implementation complexity and decoding performance, an improved method that combines our proposed MT scheme with the existing CPM-RID decoding scheme is presented. An experiment shows that both schemes can improve the bit error rate (BER) performance. Finally, we show that the MT decoding mechanism can be applied to other types of LDPC codes. We apply the MT scheme to random LDPC codes and show that it can efficiently lower the error floor.

Spatially “Mt. Fuji” coupled (SFC) low density parity check (LDPC) codes are constructed as a chain of block LDPC codes. A difference between the SFC-LDPC codes and the original spatially coupled (SC) LDPC codes is code lengths of the underlying block LDPC codes. The code length of the block LDPC code at the middle of the chain is larger than that at the end of the chain. It is experimentally confirmed that the bit error probability in the error floor region of the SFC-LDPC code is lower than that of the SC-LDPC code whose code length and design rate are the same as those of the SFC-LDPC code. In this letter, we calculate the weight distribution of the SFC-LDPC code and try to explain causes of the low bit error rates of the SFC-LDPC code.

In this letter, efficient closed-form formulas for the exact and asymptotic average bit error probability (ABEP) of space shift keying (SSK) systems are derived over Rayleigh fading channels with imperfect channel state information (CSI). Specifically, for a generic 2×NR multiple-input multiple-output (MIMO) system with the maximum likelihood (ML) detection, the impact of imperfect CSI is taken into consideration in terms of two types of channel estimation errors with the fixed variance and the variance as a function of the number of pilot symbols and signal-to-noise ratio (SNR). Then, the explicit evaluations of the bit error floor (BEF) and asymptotic SNR loss are carried out based on the derived asymptotic ABEP formula, which accounts for the impact of imperfect CSI on the SSK system. The numerical results are presented to validate the exactness of our theoretical analysis.

In this letter, we present a new scheme to find small fundamental instantons (SFIs) of regular low-density parity-check (LDPC) codes for the linear programming (LP) decoding over the binary symmetric channel (BSC). Based on the fact that each instanton-induced graph (IIG) contains at least one short cycle, we determine potential instantons by constructing possible IIGs which contain short cycles and additional paths connected to the cycles. Then we identify actual instantons from potential ones under the LP decoding. Simulation results on some typical LDPC codes show that our scheme is effective, and more instantons can be obtained by the proposed scheme when compared with the existing instanton search method.

In this paper, we propose a message passing decoding algorithm which lowers decoding error rates in the error floor regions for non-binary low-density parity-check (LDPC) codes transmitted over the binary erasure channel (BEC) and the memoryless binary-input output-symmetric (MBIOS) channels. In the case for the BEC, this decoding algorithm is a combination with belief propagation (BP) decoding and maximum a posteriori (MAP) decoding on zigzag cycles, which cause decoding errors in the error floor region. We show that MAP decoding on the zigzag cycles is realized by means of a message passing algorithm. Moreover, we extend this decoding algorithm to the MBIOS channels. Simulation results demonstrate that the decoding error rates in the error floor regions by the proposed decoding algorithm are lower than those by the BP decoder.

In this paper, we compare the decoding error rates in the error floors for non-binary low-density parity-check (LDPC) codes over general linear groups with those for non-binary LDPC codes over finite fields transmitted through the q-ary memoryless symmetric channels under belief propagation decoding. To analyze non-binary LDPC codes defined over both the general linear group GL(m, F2) and the finite field F2m, we investigate non-binary LDPC codes defined over GL(m3, F2m4). We propose a method to lower the error floors for non-binary LDPC codes. In this analysis, we see that the non-binary LDPC codes constructed by our proposed method defined over general linear group have the same decoding performance in the error floors as those defined over finite field. The non-binary LDPC codes defined over general linear group have more choices of the labels on the edges which satisfy the condition for the optimization.

In this paper, we investigate the error floors of the non-binary low-density parity-check codes transmitted over the binary erasure channels under belief propagation decoding. We propose a method to improve the decoding erasure rates in the error floors by optimizing labels in zigzag cycles in the Tanner graphs of codes. Furthermore, we give lower bounds on the bit and the symbol erasure rates in the error floors. The simulation results show that the presented lower bounds are tight for the codes designed by the proposed method.

Irregular low-density parity-check (LDPC) codes generally have good decoding performance in the waterfall region, but they exhibit higher error floors than regular ones. In this letter, we present a hybrid method, which combines code construction and the iterative decoding algorithm, to tackle this problem. Simulation results show that the proposed scheme decreases the error floor significantly for irregular LDPC codes over binary-input additive white Gaussian noise (BIAWGN) channel.

In this paper, we investigate the error floors of non-binary low-density parity-check (LDPC) codes transmitted over the memoryless binary-input output-symmetric (MBIOS) channels. We provide a necessary and sufficient condition for successful decoding of zigzag cycle codes over the MBIOS channel by the belief propagation decoder. We consider an expurgated ensemble of non-binary LDPC codes by using the above necessary and sufficient condition, and hence exhibit lower error floors. Finally, we show lower bounds of the error floors for the expurgated LDPC code ensembles over the MBIOS channels.

In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.

Trapping sets have been identified as one of the main factors causing error floors of low-density parity-check (LDPC) codes at high SNR values. By adding several new rows to the original parity-check matrix, a novel method is proposed to eliminate small trapping sets in the LDPC code's Tanner graph. Based on this parity-check matrix extension, we design new codes with low error floors from the original irregular LDPC codes. Simulation results show that the proposed method can lower the error floors of irregular LDPC codes significantly at high SNR values over AWGN channels.

In this paper we look at the serial concatenation of short linear block codes with a rate-1 recursive convolutional encoder, with a goal of designing high-rate codes with low error floor. We observe that under turbo-style decoding the error floor of the concatenated codes with extended Hamming codes is due to detectable errors in many cases. An interleaver design addressing this is proposed in this paper and its effectiveness is verified numerically. We next examine the use of extended BCH codes of larger minimum distance, resulting in an improved weight spectrum of the overall code. Reduced complexity list decoding is used to decode the BCH codes in order to obtain low decoding complexity for a negligible loss in performance.

Irregular LDPC codes can achieve better error rate performance than regular LDPC codes. However, irregular LDPC codes have higher error floors than regular LDPC codes. The Ordered Statistic Decoding (OSD) algorithm achieves approximate Maximum Likelihood (ML) decoding. ML decoding is effective to lower error floors. However, the OSD estimates satisfy the parity check equation of the LDPC code even the estimates are wrong. Hybrid decoder combining LLR-BP decoding algorithm and the OSD algorithm cannot also lower error floors, because wrong estimates also satisfy the LDPC parity check equation. We proposed the concatenated code constructed with an inner irregular LDPC code and an outer Cyclic Redundancy Check (CRC). Owing to CRC, we can detect wrong codewords from OSD estimates. Our CRC-LDPC code with hybrid decoder can lower error floors in an AWGN channel. In wireless communications, we cannot neglect the effects of the channel. The OSD algorithm needs the ordering of each bit based on the reliability. The Channel State Information (CSI) is used for deciding reliability of each bit. In this paper, we evaluate the Block Error Rate (BLER) of the CRC-LDPC code with hybrid decoder in a fast fading channel with perfect and imperfect CSIs where 'imperfect CSI' means that the distribution of channel and those statistical average of the fading amplitudes are known at the receiver. By computer simulation, we show that the CRC-LDPC code with hybrid decoder can lower error floors than the conventional LDPC code with hybrid decoder in the fast fading channel with perfect and imperfect CSIs. We also show that combining error detection with the OSD algorithm is effective not only for lowering the error floor but also for reducing computational complexity of the OSD algorithm.

In this paper, we define a stopping set of turbo codes with the iterative decoding in the binary erasure channel. Based on the stopping set analysis, we study the block and bit erasure probabilities of turbo codes and the performance degradation of the iterative decoding against the maximum-likelihood decoding. The error floor performance of turbo codes with the iterative decoding is dominated by the small stopping sets. The performance degradation of the iterative decoding is negligible in the error floor region, so the error floor performance is asymptotically dominated by the low weight codewords.

Irregular Low-Density Parity-Check (LDPC) codes generally achieve better performance than regular LDPC codes at low Eb/N0 values. They have, however, higher error floors than regular LDPC codes. With respect to the construction of the irregular LDPC code, it can achieve the trade-off between the performance degradation of low Eb/N0 region and lowering error floor. It is known that a decoding algorithm can achieve very good performance if it combines the Ordered Statistic Decoding (OSD) algorithm and the Log Likelihood Ratio-Belief Propagation (LLR-BP) decoding algorithm. Unfortunately, all the codewords obtained by the OSD algorithm satisfy the parity check equation of the LDPC code. While we can not use the parity check equation of the LDPC code to stop the decoding process, the wrong codeword that satisfies the parity check equation raises the error floor. Once a codeword that satisfies the parity check equation is generated by the LLR-BP decoding algorithm, we regard that codeword as the final estimate and halt decoding; the OSD algorithm is not performed. In this paper, we propose a new encoding/decoding scheme to lower the error floor created by irregular LDPC codes. The proposed encoding scheme encodes information bits by Cyclic Redundancy Check (CRC) and LDPC code. The proposed decoding scheme, which consists of the LLR-BP decoding, CRC check, and OSD decoding, detects errors in the codewords obtained by the LLR-BP decoding algorithm and the OSD decoding algorithm using the parity check equations of LDPC codes and CRC. Computer simulations show that the proposed encoding/decoding scheme can lower the error floor of irregular LDPC codes.