Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages

Takeshi YUASA; Tamotsu NISHINO; Hideyuki OH-HASHI

doi:10.1093/ietele/e88-c.7.1401

Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages

Takeshi YUASA, Tamotsu NISHINO, Hideyuki OH-HASHI

Full Text Views

0

Share
Cite this

Summary :

In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposed formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.

Publication: IEICE TRANSACTIONS on Electronics Vol.E88-C No.7 pp.1401-1405

Publication Date: 2005/07/01

Publicized

Online ISSN

DOI: 10.1093/ietele/e88-c.7.1401

Type of Manuscript: Special Section PAPER (Special Section on Recent Technologies of Microwave and Millimeter-Wave Devices Focusing on Miniaturization and Advancement in Performance with Their Applications)

Category: Passive Circuits

Cite this

Copy

Takeshi YUASA, Tamotsu NISHINO, Hideyuki OH-HASHI, "Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages" in IEICE TRANSACTIONS on Electronics, vol. E88-C, no. 7, pp. 1401-1405, July 2005, doi: 10.1093/ietele/e88-c.7.1401.
Abstract: In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposed formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.7.1401/_p

Copy

@ARTICLE{e88-c_7_1401,
author={Takeshi YUASA, Tamotsu NISHINO, Hideyuki OH-HASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages},
year={2005},
volume={E88-C},
number={7},
pages={1401-1405},
abstract={In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposed formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.},
keywords={},
doi={10.1093/ietele/e88-c.7.1401},
ISSN={},
month={July},}

Copy

TY - JOUR
TI - Simple Design Formula for Parallel Plate Mode Suppression by Ground Via-Holes in Multi-Layered Packages
T2 - IEICE TRANSACTIONS on Electronics
SP - 1401
EP - 1405
AU - Takeshi YUASA
AU - Tamotsu NISHINO
AU - Hideyuki OH-HASHI
PY - 2005
DO - 10.1093/ietele/e88-c.7.1401
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2005
AB - In a multi-layered RF circuit, it is important to avoid unexpected coupling caused by a parallel plate mode excited between different ground layers. Ground via-holes that short-circuit different ground layers are used for suppressing this mode. Quantitative evaluation of relations between suppression effect and ground via-hole disposition is required for optimal design. In this paper, a simple design formula that describes the suppression ratio is derived by mode-matching technique. The results of comparison with an FEM simulation validate our proposed formula. It is shown that the technique is indispensable for designing optimal disposition of via-holes to minimize the area of the ground via-holes for desired performance.
ER -