A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology

Daisuke MIZOGUCHI; Noriyuki MIURA; Takayasu SAKURAI; Tadahiro KURODA

doi:10.1093/ietele/e89-c.3.320

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology

Daisuke MIZOGUCHI, Noriyuki MIURA, Takayasu SAKURAI, Tadahiro KURODA

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A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm² will be obtained.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.320-326

Publication Date: 2006/03/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.3.320

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)

Category: Interface and Interconnect Techniques

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Daisuke MIZOGUCHI, Noriyuki MIURA, Takayasu SAKURAI, Tadahiro KURODA, "A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 3, pp. 320-326, March 2006, doi: 10.1093/ietele/e89-c.3.320.
Abstract: A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm² will be obtained.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.320/_p

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@ARTICLE{e89-c_3_320,
author={Daisuke MIZOGUCHI, Noriyuki MIURA, Takayasu SAKURAI, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology},
year={2006},
volume={E89-C},
number={3},
pages={320-326},
abstract={A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm² will be obtained.},
keywords={},
doi={10.1093/ietele/e89-c.3.320},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 320
EP - 326
AU - Daisuke MIZOGUCHI
AU - Noriyuki MIURA
AU - Takayasu SAKURAI
AU - Tadahiro KURODA
PY - 2006
DO - 10.1093/ietele/e89-c.3.320
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm² will be obtained.
ER -