This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.

The increase of recent non-recurrent engineering cost (design, mask and test cost) have made large System-on-Chip (SoC) difficult to develop especially with advanced technology. We radically explore an approach for cheap and flexible chip stacking by using Inductive coupling ThruChip Interface (TCI). In order to connect a large number of small chips for building a large scale system, novel chip stacking methods called the linear stacking and staggered stacking are proposed. They enable the system to be extended to x or/and y dimensions, not only to z dimension. Here, a novel chip staking layout, and its deadlock-free routing design for the case using single-core chips and multi-core chips are shown. The network with 256 nodes formed by the proposed stacking improves the latency of 2D mesh by 13.8% and the performance of NAS Parallel Benchmarks by 5.4% on average compared to that of 2D mesh.

ThruChip interface (TCI) is an emerging wireless interface in three-dimensional (3-D) integrated circuit (IC) technology. However, the TCI physical design guidelines remain unclear. In this paper, a ThruChip test chip is designed and fabricated for design guidelines exploration. Three inductive coupling interface physical design scenarios, baseline, power mesh, and dummy metal fill, are deployed in the test chip. In the baseline scenario, the test chip measurement results show that thinning chip or enlarging coil dimension can further reduce TCI power. The power mesh scenario shows that the eddy current on power mesh can dramatically reduce magnetic pulse signal and thus possibly cause TCI to fail. A power mesh splitting method is proposed to effectively suppress eddy current impact while minimizing power mesh structure impact. The simulation results show that the proposed method can recover 77% coupling coefficient loss while only introducing additional 0.5% IR-drop. In dummy metal fill case, dummy metal fill enclosed within TCI coils have no impact on TCI transmission and thus are ignorable.

Wafer-level testing is a well established solution for detecting manufacturing errors and removing non-functional devices early in the fabrication process. Recently this technique has been facing a number of challenges, resulting from increased complexity of devices under test, larger number and higher density of pads or bumps, application of mechanically fragile materials, such as low-k dielectrics, and ever developing packaging technologies. Most of these difficulties originate from the use of mechanical probes, as they limit testing speed, impose performance limitations and add reliability issues. Earlier work focused on relaxing these constraints by removing mechanical probes for data transmission and DC signal measurement and replacing them with non-contact interfaces. In this paper we extend this concept by adding a capability of transferring power wirelessly, enabling non-contact wafer-level testing. In addition to further improvements in the performance and reliability, this solution enables new testing scenarios such as probing wafers from their backside. The proposed system achieves 6 W/25 mm2 power transfer density over a distance of up to 0.32 mm, making it suitable for non-contact wafer-level testing of medium performance CMOS integrated circuits.

A Real-time Capacitor Compensation (RCC) scheme is proposed for low power and continuous communication in the wearable inductive coupling transceiver. Since inductance values of wearable inductor vary dynamically with deterioration of its communication characteristics, the inductance value is monitored and its resonance frequency is adjusted by additive parallel/serial capacitors in real time. RLC Bridge for detection of the inductance variations and the Dual-edge Sampling Comparator for recognition of the variance direction are proposed. It is implemented in a 0.18 µm CMOS technology, and it occupies a 12.7 mm2 chip area. The proposed transceiver consumes only 426.6 µW at 4 Mbps data rate. The compensation time takes 4.78 µs, including 3 µs of detection and 1.78 µs for compensation process in worst case.

A 2.45-GHz-band small passive radio-frequency identification (RFID) tag consists of a small loop antenna and chip, and its size is several millimeters. Because of the tag's poor impedance-matching characteristic and radiation efficiency, an ordinary reader has difficulty reading it. We propose a new technique for reading the tag that involves installing a square half-wavelength meander-line conductor on the reader as an adapter and placing the adapter in the vicinity of the tag, and verify the effectiveness of the technique by simulation and experiment. Moreover, characteristics of simultaneous read of the small RFID tags by the proposed reading technique are revealed by simulation and experimental results.

A wireless transceiver utilizing inductive coupling has been proposed for communication between chips in system in a package. This transceiver can achieve high-speed communication by using two-dimensional channel arrays. To increase the total bandwidth in the channel arrays, the density of the transceiver should be improved, which means that the inductor size should be scaled down. This paper discusses the scaling theory based on a constant magnetic field rule. By decreasing the chip thickness with the process scaling of 1/α, the inductor size can be scaled to 1/α and the data rate can be increased by α. As a result, the number of aggregated channels can be increased by α2 and the aggregated data bandwidth can be increased by α3. The scaling theory is verified by simulations and experiments in 350, 250, 180, and 90 nm CMOS.

A daisy chain of current-driven transmitters in inductive-coupling complementary metal oxide semiconductor (CMOS) links is presented. Transmitter power can be reduced since current is reused by multiple transmitters. Eight transceivers are arranged with a pitch of 20 µm in 0.18 µm CMOS. Transmitter power is reduced by 35% without sacrificing either the data rate (1 Gb/s/ch) or BER (<10-12) by using a 4-transmitter daisy chain. A coding technique for efficient use of daisy chain transmitters is also proposed. With the proposed coding technique, additional power reduction can be achieved.

A wireless interface for stacked chips in System-in-a-Package is presented. The interface utilizes inductive coupling between metal inductors. S21 parameters of the inductive coupling are measured between chips stacked in face-up for the first time. Calculations from a theoretical model have good agreement with the measurements. A transceiver circuit for Non-Return-to-Zero signaling is developed to reduce power dissipation. The transceiver is implemented in a test chip fabricated in 0.35 µm CMOS and the chips are stacked in face-up. The chips communicate through the transceiver at 1.2 Gb/s/ch with 46 mW power dissipation at 3.3 V over 300 µm distance. A scaling scenario is derived based on the theoretical model and measurement results. It indicates that, if the communication distance is reduced to 13 µm in 70 nm CMOS, 34 Tbps/mm2 will be obtained.

A highly collision-resistive RFID system multiplexes communications between thousands of tags and a single reader in combination with time-domain multiplexing code division multiple access (TD-CDMA), CRC error detection, and re-transmission for error recovery. The collision probability due to a random selection of CDMA codes and TDMA channels bounds the number of IDs successfully transmitted to a reader during a limited time frame. However, theoretical analysis showed that the re-transmission greatly reduced the collision probability and that an ID error rate of 2.510-9 could be achieved when 1,000 ID tags responded within a time frame of 400 msec in ideal communication channels. The proposed collision-resistive communication scheme for a thousand multiplexed channels was modeled on a discrete-time digital expression and an FPGA-based emulator was built to evaluate a practical ID error rate under the presence of background noise in communication channels. To achieve simple anti-noise communication in a multiple-response RFID system, as well as unurged re-transmission of ID data, adjusting of correlator thresholds provides a significant improvement to the error rate. Thus, the proposed scheme does not require a reader to request ID transmission to erroneously responding tags. A reader also can lower noise influence by using correlator thresholds, since the scheme multiplexes IDs by CDMA-based communication. The effectiveness of the re-transmission was confirmed experimentally even in noisy channels, and the ID error rate derived from the emulation was 1.910-5. The emulation was useful for deriving an optimum set of RFID system parameters to be used in the design of mixed analog and digital integrated circuits for RFID communication.

This study presents a method of realizing second order band-pass filters with planar inductive π-network. The proposed filter is more flexible in practical implementation than those using magnetic or electric coupling methods. Electromagnetic simulation results show that the bandwidth of the filter is quite insensitive to the variation in substrate thicknesses and physical layout. A 5.2 GHz filter prototype is designed and fabricated. The measured insertion loss is less than 2.3 dB in the designed pass band and the attenuations at the stop bands are all greater than 30 dB.