Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use

Masao HOTTA; Tatsuji MATSUURA

doi:10.1093/ietele/e89-c.6.664

Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use

Masao HOTTA, Tatsuji MATSUURA

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Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.664-672

Publication Date: 2006/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.6.664

Type of Manuscript: Special Section INVITED PAPER (Special Section on Analog Circuit and Device Technologies)

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Masao HOTTA, Tatsuji MATSUURA, "Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 6, pp. 664-672, June 2006, doi: 10.1093/ietele/e89-c.6.664.
Abstract: Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.664/_p

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@ARTICLE{e89-c_6_664,
author={Masao HOTTA, Tatsuji MATSUURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use},
year={2006},
volume={E89-C},
number={6},
pages={664-672},
abstract={Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.},
keywords={},
doi={10.1093/ietele/e89-c.6.664},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use
T2 - IEICE TRANSACTIONS on Electronics
SP - 664
EP - 672
AU - Masao HOTTA
AU - Tatsuji MATSUURA
PY - 2006
DO - 10.1093/ietele/e89-c.6.664
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - Analog-to-Digital converters (ADCs) for video applications have made exciting progress in miniaturization and power reduction in the past 20 years. This paper mainly describes the key technologies for miniaturization and power reduction of 10-bit video-frequency ADCs. By reviewing useful architectures and circuit schemes for video-frequency ADCs, self-calibration techniques and interleaving techniques are surveyed. The subranging pipeline look-ahead ADC architecture is introduced. It has a potential for reducing power consumption and improving conversion rate when minute deep submicron CMOS devices are used with low supply voltage.
ER -