An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity

Koichiro NOGUCHI; Makoto NAGATA

doi:10.1093/ietele/e89-c.6.761

An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity

Koichiro NOGUCHI, Makoto NAGATA

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A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a current-mode sample and a hold circuit that is connected to a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30 µm120 µm silicon area. We also showed that such signal monitor circuits can be tailored to sense of power-supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltage domain waveform acquisition for the purpose of the in-depth study of digital signal integrity.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.6 pp.761-768

Publication Date: 2006/06/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.6.761

Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies)

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Koichiro NOGUCHI, Makoto NAGATA, "An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 6, pp. 761-768, June 2006, doi: 10.1093/ietele/e89-c.6.761.
Abstract: A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a current-mode sample and a hold circuit that is connected to a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30 µm120 µm silicon area. We also showed that such signal monitor circuits can be tailored to sense of power-supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltage domain waveform acquisition for the purpose of the in-depth study of digital signal integrity.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.6.761/_p

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@ARTICLE{e89-c_6_761,
author={Koichiro NOGUCHI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity},
year={2006},
volume={E89-C},
number={6},
pages={761-768},
abstract={A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a current-mode sample and a hold circuit that is connected to a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30 µm120 µm silicon area. We also showed that such signal monitor circuits can be tailored to sense of power-supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltage domain waveform acquisition for the purpose of the in-depth study of digital signal integrity.},
keywords={},
doi={10.1093/ietele/e89-c.6.761},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - An On-Chip Multi-Channel Rail-to-Rail Signal Monitoring Technique for Sub-100-nm Digital Signal Integrity
T2 - IEICE TRANSACTIONS on Electronics
SP - 761
EP - 768
AU - Koichiro NOGUCHI
AU - Makoto NAGATA
PY - 2006
DO - 10.1093/ietele/e89-c.6.761
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2006
AB - A compact on-chip signal monitor circuit uses voltage mode sensing by a source follower circuit with small input device geometry, followed by a current-mode sample and a hold circuit that is connected to a shared current output bus. A prototype signal monitor circuit demonstrated a 1.1-GHz effective bandwidth for 1.0-V full-swing digital signals in a 90-nm CMOS technology, where the monitor used 2.5-V I/O CMOS transistors and occupied a 30 µm120 µm silicon area. We also showed that such signal monitor circuits can be tailored to sense of power-supply, ground, as well as full-swing logic signal wirings, and form an array with a single current output. Therefore, an on-chip multi-channel signal monitor enables multiple-points as well as multiple-voltage domain waveform acquisition for the purpose of the in-depth study of digital signal integrity.
ER -