A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution

Chang-Kyung SEONG; Seung-Woo LEE; Woo-Young CHOI

doi:10.1093/ietele/e90-c.1.165

A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution

Chang-Kyung SEONG, Seung-Woo LEE, Woo-Young CHOI

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A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm² and consumes 17.8 mW.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.1 pp.165-170

Publication Date: 2007/01/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.1.165

Type of Manuscript: PAPER

Category: Electronic Circuits

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Chang-Kyung SEONG, Seung-Woo LEE, Woo-Young CHOI, "A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 1, pp. 165-170, January 2007, doi: 10.1093/ietele/e90-c.1.165.
Abstract: A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm² and consumes 17.8 mW.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.1.165/_p

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@ARTICLE{e90-c_1_165,
author={Chang-Kyung SEONG, Seung-Woo LEE, Woo-Young CHOI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution},
year={2007},
volume={E90-C},
number={1},
pages={165-170},
abstract={A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm² and consumes 17.8 mW.},
keywords={},
doi={10.1093/ietele/e90-c.1.165},
ISSN={1745-1353},
month={January},}

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TY - JOUR
TI - A 1.25-Gb/s Digitally-Controlled Dual-Loop Clock and Data Recovery Circuit with Enhanced Phase Resolution
T2 - IEICE TRANSACTIONS on Electronics
SP - 165
EP - 170
AU - Chang-Kyung SEONG
AU - Seung-Woo LEE
AU - Woo-Young CHOI
PY - 2007
DO - 10.1093/ietele/e90-c.1.165
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2007
AB - A new 1.25-Gb/s digitally-controlled dual-loop clock and data recovery circuit is realized. To overcome jitter problems caused by the phase resolution limit, the CDR has two phase generation stages: coarse generation by a phase interpolator and fine generation by a variable delay buffer. The performance of the proposed CDR was verified by behavioral and transistor-level simulations. A prototype CDR chip fabricated with 0.18 µm CMOS process shows error-free operation for 400 ppm frequency offset. The chip occupies 165255 µm² and consumes 17.8 mW.
ER -