This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90
Hiroyuki ITO
Hideyuki SUGITA
Kenichi OKADA
Tatsuya ITO
Kazuhisa ITOI
Masakazu SATO
Ryozo YAMAUCHI
Kazuya MASU
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Hiroyuki ITO, Hideyuki SUGITA, Kenichi OKADA, Tatsuya ITO, Kazuhisa ITOI, Masakazu SATO, Ryozo YAMAUCHI, Kazuya MASU, "Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 3, pp. 641-643, March 2007, doi: 10.1093/ietele/e90-c.3.641.
Abstract: This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.3.641/_p
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@ARTICLE{e90-c_3_641,
author={Hiroyuki ITO, Hideyuki SUGITA, Kenichi OKADA, Tatsuya ITO, Kazuhisa ITOI, Masakazu SATO, Ryozo YAMAUCHI, Kazuya MASU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology},
year={2007},
volume={E90-C},
number={3},
pages={641-643},
abstract={This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90
keywords={},
doi={10.1093/ietele/e90-c.3.641},
ISSN={1745-1353},
month={March},}
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TY - JOUR
TI - Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 641
EP - 643
AU - Hiroyuki ITO
AU - Hideyuki SUGITA
AU - Kenichi OKADA
AU - Tatsuya ITO
AU - Kazuhisa ITOI
AU - Masakazu SATO
AU - Ryozo YAMAUCHI
AU - Kazuya MASU
PY - 2007
DO - 10.1093/ietele/e90-c.3.641
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2007
AB - This paper proposes high-Q distributed constant passive devices using wafer-level chip scale package (WL-CSP) technology, which can be realized on a Si CMOS chip. A 90
ER -