Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories

Kazuo OTSUGA; Hideaki KURATA; Satoshi NODA; Yoshitaka SASAGO; Tsuyoshi ARIGANE; Tetsufumi KAWAMURA; Takashi KOBAYASHI

doi:10.1093/ietele/e90-c.4.772

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories

Kazuo OTSUGA, Hideaki KURATA, Satoshi NODA, Yoshitaka SASAGO, Tsuyoshi ARIGANE, Tetsufumi KAWAMURA, Takashi KOBAYASHI

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We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each V_th level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.772-778

Publication Date: 2007/04/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.4.772

Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)

Category: Memory

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Kazuo OTSUGA, Hideaki KURATA, Satoshi NODA, Yoshitaka SASAGO, Tsuyoshi ARIGANE, Tetsufumi KAWAMURA, Takashi KOBAYASHI, "Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 4, pp. 772-778, April 2007, doi: 10.1093/ietele/e90-c.4.772.
Abstract: We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each V_th level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.772/_p

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@ARTICLE{e90-c_4_772,
author={Kazuo OTSUGA, Hideaki KURATA, Satoshi NODA, Yoshitaka SASAGO, Tsuyoshi ARIGANE, Tetsufumi KAWAMURA, Takashi KOBAYASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories},
year={2007},
volume={E90-C},
number={4},
pages={772-778},
abstract={We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each V_th level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.},
keywords={},
doi={10.1093/ietele/e90-c.4.772},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories
T2 - IEICE TRANSACTIONS on Electronics
SP - 772
EP - 778
AU - Kazuo OTSUGA
AU - Hideaki KURATA
AU - Satoshi NODA
AU - Yoshitaka SASAGO
AU - Tsuyoshi ARIGANE
AU - Tetsufumi KAWAMURA
AU - Takashi KOBAYASHI
PY - 2007
DO - 10.1093/ietele/e90-c.4.772
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each V_th level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.
ER -