A 1-Gb AG-AND flash memory has been fabricated using 0.13-µm CMOS technology, resulting in a cell area of 0.104 µm2 and a chip area of 95.2 mm2. By applying constant-charge-injection programming and source-line-select programming, a fast page programming time of 600 µs is achieved. The four-bank operation attains a fast programming throughput of 10 MB/s in multilevel flash memories. The compact SRAM write buffers reduce the chip area penalty. A rewrite throughput of 8.3 MB/s is achieved by means of the RAM-write operation during the erase mode.

We developed a selective-capacitance constant-charge-injection programming (CCIP) scheme to achieve high programming throughput in multilevel assist-gate (AG)-AND flash memories. In the conventional CCIP scheme, only one type of capacitance for storing programming charge was used for all levels of multilevel cells. The proposed scheme utilized multiple types of capacitance to minimize the programming time of all levels by using optimized capacitance values for each Vth level. In 4-Gbit AG-AND flash memories, a local bit line capacitance is utilized for mid-level programming, and the sum of local and global bit line capacitance is utilized for top-level programming. In addition, we developed a verify-less programming scheme which reduces top-level programming time because it is not necessary to verify the top-level of multilevel cells in AND flash memory architecture. A programming throughput of 10 MB/s is achieved using the proposed schemes. This is 1.6 times faster than the throughput with conventional CCIP.

This paper reviews process, device and circuit technologies of high-density flash memories, whose market has grown explosively as bridge media. In this memory, programming throughput as well as low bit costs is critical issue. To meet the requirements, we have developed multi-level AG (Assist Gate)-AND type flash memory with small effective cell size and 10 MB/s programming throughput. We clarify three challenges to the multilevel flash memory in terms of operation method, high reliability for data retention, and high-speed multilevel programming. Future trends of high-density flash memories are also discussed.

A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F2 of 0.0162 µm2, resulting in a chip size of 126 mm2. Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10 MB/s.

A design methodology optimizing constant-charge-injection programming (CCIP) for assist-gate (AG)-AND flash memories is proposed. Transient circuit simulations using an array-level model including lucky electron model (LEM) current source describing hot electron physics enables a concept design over the whole memory-string in advance of wafer manufacturing. The dynamic programming behaviors of various CCIP sequences, obtained by circuit simulations using the model is verified with the measurement results of 90-nm AG-AND flash memory, and we confirmed that the simulation results sufficiently agree with the measurement, considering the simulation results give optimum bias AG voltage approximately within 0.2 V error. Then, we have applied the model to a conceptual design and have obtained optimum bit line capacitance value and CCIP sequence those are the most important issues involved in high-throughput programming for an AG-AND array.