Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

Hasitha Muthumala WAIDYASOORIYA; Weisheng CHONG; Masanori HARIYAMA; Michitaka KAMEYAMA

doi:10.1093/ietele/e91-c.4.517

Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment

Hasitha Muthumala WAIDYASOORIYA, Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA

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Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory bits cause significant overhead in area and power consumption. This paper presents novel architecture of a switch element to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 µm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. Moreover, novel CAD process that exploits the redundancy in configuration data, is proposed to support the MC-FPGA architecture.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.517-525

Publication Date: 2008/04/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.4.517

Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)

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Hasitha Muthumala WAIDYASOORIYA, Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA, "Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 4, pp. 517-525, April 2008, doi: 10.1093/ietele/e91-c.4.517.
Abstract: Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory bits cause significant overhead in area and power consumption. This paper presents novel architecture of a switch element to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 µm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. Moreover, novel CAD process that exploits the redundancy in configuration data, is proposed to support the MC-FPGA architecture.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.517/_p

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@ARTICLE{e91-c_4_517,
author={Hasitha Muthumala WAIDYASOORIYA, Weisheng CHONG, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment},
year={2008},
volume={E91-C},
number={4},
pages={517-525},
abstract={Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory bits cause significant overhead in area and power consumption. This paper presents novel architecture of a switch element to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 µm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. Moreover, novel CAD process that exploits the redundancy in configuration data, is proposed to support the MC-FPGA architecture.},
keywords={},
doi={10.1093/ietele/e91-c.4.517},
ISSN={1745-1353},
month={April},}

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TY - JOUR
TI - Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment
T2 - IEICE TRANSACTIONS on Electronics
SP - 517
EP - 525
AU - Hasitha Muthumala WAIDYASOORIYA
AU - Weisheng CHONG
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 2008
DO - 10.1093/ietele/e91-c.4.517
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - Dynamically-programmable gate arrays (DPGAs) promise lower-cost implementations than conventional field-programmable gate arrays (FPGAs) since they efficiently reuse limited hardware resources in time. One of the typical DPGA architectures is a multi-context FPGA (MC-FPGA) that requires multiple memory bits per configuration bit to realize fast context switching. However, this additional memory bits cause significant overhead in area and power consumption. This paper presents novel architecture of a switch element to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18 µm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310 MHz and 272 MHz, respectively. Moreover, novel CAD process that exploits the redundancy in configuration data, is proposed to support the MC-FPGA architecture.
ER -