A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI

Yusuke OHTOMO; Hiroshi KOIZUMI; Kazuyoshi NISHIMURA; Masafumi NOGAWA

doi:10.1093/ietele/e91-c.4.655

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI

Yusuke OHTOMO, Hiroshi KOIZUMI, Kazuyoshi NISHIMURA, Masafumi NOGAWA

Full Text Views

0

Share
Cite this

Summary :

This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.655-661

Publication Date: 2008/04/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.4.655

Type of Manuscript: PAPER

Category: Integrated Electronics

Cite this

Copy

Yusuke OHTOMO, Hiroshi KOIZUMI, Kazuyoshi NISHIMURA, Masafumi NOGAWA, "A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 4, pp. 655-661, April 2008, doi: 10.1093/ietele/e91-c.4.655.
Abstract: This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.
URL: https://globals.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.655/_p

Copy

@ARTICLE{e91-c_4_655,
author={Yusuke OHTOMO, Hiroshi KOIZUMI, Kazuyoshi NISHIMURA, Masafumi NOGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI},
year={2008},
volume={E91-C},
number={4},
pages={655-661},
abstract={This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.},
keywords={},
doi={10.1093/ietele/e91-c.4.655},
ISSN={1745-1353},
month={April},}

Copy

TY - JOUR
TI - A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-µm CMOS/SOI
T2 - IEICE TRANSACTIONS on Electronics
SP - 655
EP - 661
AU - Yusuke OHTOMO
AU - Hiroshi KOIZUMI
AU - Kazuyoshi NISHIMURA
AU - Masafumi NOGAWA
PY - 2008
DO - 10.1093/ietele/e91-c.4.655
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G.958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-µm fully depleted CMOS/SOI. The CDR shows a wide capture range of 140 MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85 and with the supply voltage variation of 6%.
ER -